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A64: Implement SRI (vector)

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Lioncash 2018-04-07 23:54:14 -04:00 committed by MerryMage
parent 11005cfe26
commit 2db032ac83
2 changed files with 27 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -806,7 +806,7 @@ INST(USHR_2, "USHR", "0Q101
INST(USRA_2, "USRA", "0Q1011110IIIIiii000101nnnnnddddd")
INST(URSHR_2, "URSHR", "0Q1011110IIIIiii001001nnnnnddddd")
INST(URSRA_2, "URSRA", "0Q1011110IIIIiii001101nnnnnddddd")
//INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")
INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd")
INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd")
//INST(SQSHLU_2, "SQSHLU", "0Q1011110IIIIiii011001nnnnnddddd")
//INST(UQSHL_imm_2, "UQSHL (immediate)", "0Q1011110IIIIiii011101nnnnnddddd")

26
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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@ -304,6 +304,32 @@ bool TranslatorVisitor::USHLL(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
return true;
}
bool TranslatorVisitor::SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();
}
if (!Q && immh.Bit<3>()) {
return ReservedValue();
}
const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
const size_t datasize = Q ? 128 : 64;
const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend<u8>());
const u64 mask = shift_amount == esize ? 0 : Common::Ones<u64>(esize) >> shift_amount;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vd);
const IR::U128 shifted = ir.VectorLogicalShiftRight(esize, operand1, shift_amount);
const IR::U128 mask_vec = ir.VectorBroadcast(esize, I(esize, mask));
const IR::U128 result = ir.VectorOr(ir.VectorAnd(operand2, ir.VectorNot(mask_vec)), shifted);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (immh == 0b0000) {
return DecodeError();