thumb32: Implement CMN (reg)
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3 changed files with 17 additions and 1 deletions
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@ -39,7 +39,7 @@ INST(thumb32_ORN_reg, "ORN (reg)", "11101010011Snnnn0vvvdd
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INST(thumb32_TEQ_reg, "TEQ (reg)", "111010101001nnnn0vvv1111vvttmmmm")
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INST(thumb32_EOR_reg, "EOR (reg)", "11101010100Snnnn0vvvddddvvttmmmm")
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INST(thumb32_PKH, "PKH", "111010101100nnnn0vvvddddvvt0mmmm")
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//INST(thumb32_CMN_reg, "CMN (reg)", "111010110001--------1111--------")
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INST(thumb32_CMN_reg, "CMN (reg)", "111010110001nnnn0vvv1111vvttmmmm")
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//INST(thumb32_ADD_reg, "ADD (reg)", "11101011000---------------------")
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//INST(thumb32_ADC_reg, "ADC (reg)", "11101011010---------------------")
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//INST(thumb32_SBC_reg, "SBC (reg)", "11101011011---------------------")
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@ -170,4 +170,19 @@ bool ThumbTranslatorVisitor::thumb32_PKH(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2,
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_CMN_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m) {
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if (n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = ir.AddWithCarry(ir.GetRegister(n), shifted.result, ir.Imm1(0));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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} // namespace Dynarmic::A32
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@ -182,6 +182,7 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_EOR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_PKH(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<1> tb, Reg m);
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bool thumb32_CMN_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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// thumb32 data processing (modified immediate) instructions
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bool thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);
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