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A32: Implement ASIMD VSHL

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This commit is contained in:
Lioncash 2020-06-18 11:12:17 -04:00
parent 69c999bc66
commit 8b98c91ecc
3 changed files with 41 additions and 9 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -63,7 +63,7 @@ INST(asimd_SRA, "SRA", "1111001U1Diiiiiidddd000
INST(asimd_VRSHR, "VRSHR", "1111001U1Diiiiiidddd0010LQM1mmmm") // ASIMD INST(asimd_VRSHR, "VRSHR", "1111001U1Diiiiiidddd0010LQM1mmmm") // ASIMD
INST(asimd_VRSRA, "VRSRA", "1111001U1Diiiiiidddd0011LQM1mmmm") // ASIMD INST(asimd_VRSRA, "VRSRA", "1111001U1Diiiiiidddd0011LQM1mmmm") // ASIMD
//INST(asimd_VSRI, "VSRI", "111100111-vvv-------0100LB-1----") // ASIMD //INST(asimd_VSRI, "VSRI", "111100111-vvv-------0100LB-1----") // ASIMD
//INST(asimd_VSHL, "VSHL", "111100101-vvv-------0101LB-1----") // ASIMD INST(asimd_VSHL, "VSHL", "111100101Diiiiiidddd0101LQM1mmmm") // ASIMD
//INST(asimd_VSLI, "VSLI", "111100111-vvv-------0101LB-1----") // ASIMD //INST(asimd_VSLI, "VSLI", "111100111-vvv-------0101LB-1----") // ASIMD
//INST(asimd_VQSHL, "VQSHL" , "1111001U1-vvv-------011xLB-1----") // ASIMD //INST(asimd_VQSHL, "VQSHL" , "1111001U1-vvv-------011xLB-1----") // ASIMD
//INST(asimd_VSHRN, "VSHRN", "111100101-vvv-------100000-1----") // ASIMD //INST(asimd_VSHRN, "VSHRN", "111100101-vvv-------100000-1----") // ASIMD

35
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
View file

@ -25,7 +25,8 @@ IR::U128 PerformRoundingCorrection(ArmTranslatorVisitor& v, size_t esize, u64 ro
return v.ir.VectorSub(esize, shifted, round_correction); return v.ir.VectorSub(esize, shifted, round_correction);
} }
std::pair<size_t, size_t> ElementSizeAndShiftAmount(bool L, size_t imm6) { std::pair<size_t, size_t> ElementSizeAndShiftAmount(bool right_shift, bool L, size_t imm6) {
if (right_shift) {
if (L) { if (L) {
return {64, 64 - imm6}; return {64, 64 - imm6};
} }
@ -33,6 +34,15 @@ std::pair<size_t, size_t> ElementSizeAndShiftAmount(bool L, size_t imm6) {
const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3); const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3);
const size_t shift_amount = (esize * 2) - imm6; const size_t shift_amount = (esize * 2) - imm6;
return {esize, shift_amount}; return {esize, shift_amount};
} else {
if (L) {
return {64, imm6};
}
const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3);
const size_t shift_amount = imm6 - esize;
return {esize, shift_amount};
}
} }
bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm, bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm,
@ -46,7 +56,7 @@ bool ShiftRight(ArmTranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd,
return v.UndefinedInstruction(); return v.UndefinedInstruction();
} }
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(L, imm6); const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6);
const auto d = ToVector(Q, Vd, D); const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M); const auto m = ToVector(Q, Vm, M);
@ -89,4 +99,25 @@ bool ArmTranslatorVisitor::asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, b
Accumulating::Accumulate, Rounding::Round); Accumulating::Accumulate, Rounding::Round);
} }
bool ArmTranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
// Technically just a related encoding (One register and modified immediate instructions)
if (!L && Common::Bits<3, 5>(imm6) == 0) {
return UndefinedInstruction();
}
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, L, imm6);
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = ir.VectorLogicalShiftLeft(esize, reg_m, static_cast<u8>(shift_amount));
ir.SetVector(d, result);
return true;
}
} // namespace Dynarmic::A32 } // namespace Dynarmic::A32

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -456,6 +456,7 @@ struct ArmTranslatorVisitor final {
bool asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_SRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VRSHR(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
bool asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous // Advanced SIMD two register, miscellaneous
bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm); bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);