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a32_jitstate: Rename FPSCR_nzcv to fpsr_nzcv

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This commit is contained in:
MerryMage 2019-05-05 19:46:57 +01:00
parent 76f986979d
commit b3bb544bca
4 changed files with 7 additions and 7 deletions
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4
src/backend/x64/a32_emit_x64.cpp
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@ -748,7 +748,7 @@ void A32EmitX64::EmitA32SetFpscr(A32EmitContext& ctx, IR::Inst* inst) {
void A32EmitX64::EmitA32GetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) { void A32EmitX64::EmitA32GetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32(); const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
code.mov(result, dword[r15 + offsetof(A32JitState, FPSCR_nzcv)]); code.mov(result, dword[r15 + offsetof(A32JitState, fpsr_nzcv)]);
ctx.reg_alloc.DefineValue(inst, result); ctx.reg_alloc.DefineValue(inst, result);
} }
@ -761,7 +761,7 @@ void A32EmitX64::EmitA32SetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
code.shl(value, 16); code.shl(value, 16);
code.and_(value, 0xF0000000); code.and_(value, 0xF0000000);
code.mov(dword[r15 + offsetof(A32JitState, FPSCR_nzcv)], value); code.mov(dword[r15 + offsetof(A32JitState, fpsr_nzcv)], value);
} }
void A32EmitX64::EmitA32ClearExclusive(A32EmitContext&, IR::Inst*) { void A32EmitX64::EmitA32ClearExclusive(A32EmitContext&, IR::Inst*) {

2
src/backend/x64/a32_interface.cpp
View file

@ -272,7 +272,7 @@ void TransferJitState(A32JitState& dest, const A32JitState& src, bool reset_rsb)
dest.guest_MXCSR = src.guest_MXCSR; dest.guest_MXCSR = src.guest_MXCSR;
dest.fpsr_idc = src.fpsr_idc; dest.fpsr_idc = src.fpsr_idc;
dest.fpcr_mode = src.fpcr_mode; dest.fpcr_mode = src.fpcr_mode;
dest.FPSCR_nzcv = src.FPSCR_nzcv; dest.fpsr_nzcv = src.fpsr_nzcv;
if (reset_rsb) { if (reset_rsb) {
dest.ResetRSB(); dest.ResetRSB();
} else { } else {

6
src/backend/x64/a32_jitstate.cpp
View file

@ -155,10 +155,10 @@ constexpr u32 FPSCR_NZCV_MASK = 0xF0000000;
u32 A32JitState::Fpscr() const { u32 A32JitState::Fpscr() const {
ASSERT((fpcr_mode & ~FPSCR_MODE_MASK) == 0); ASSERT((fpcr_mode & ~FPSCR_MODE_MASK) == 0);
ASSERT((FPSCR_nzcv & ~FPSCR_NZCV_MASK) == 0); ASSERT((fpsr_nzcv & ~FPSCR_NZCV_MASK) == 0);
ASSERT((fpsr_idc & ~(1 << 7)) == 0); ASSERT((fpsr_idc & ~(1 << 7)) == 0);
u32 FPSCR = fpcr_mode | FPSCR_nzcv; u32 FPSCR = fpcr_mode | fpsr_nzcv;
FPSCR |= (guest_MXCSR & 0b0000000000001); // IOC = IE FPSCR |= (guest_MXCSR & 0b0000000000001); // IOC = IE
FPSCR |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE FPSCR |= (guest_MXCSR & 0b0000000111100) >> 1; // IXC, UFC, OFC, DZC = PE, UE, OE, ZE
FPSCR |= fpsr_idc; FPSCR |= fpsr_idc;
@ -170,7 +170,7 @@ u32 A32JitState::Fpscr() const {
void A32JitState::SetFpscr(u32 FPSCR) { void A32JitState::SetFpscr(u32 FPSCR) {
old_FPSCR = FPSCR; old_FPSCR = FPSCR;
fpcr_mode = FPSCR & FPSCR_MODE_MASK; fpcr_mode = FPSCR & FPSCR_MODE_MASK;
FPSCR_nzcv = FPSCR & FPSCR_NZCV_MASK; fpsr_nzcv = FPSCR & FPSCR_NZCV_MASK;
guest_MXCSR = 0; guest_MXCSR = 0;
// Exception masks / enables // Exception masks / enables

2
src/backend/x64/a32_jitstate.h
View file

@ -71,7 +71,7 @@ struct A32JitState {
u32 fpsr_qc = 0; // Dummy value u32 fpsr_qc = 0; // Dummy value
u32 fpsr_idc = 0; u32 fpsr_idc = 0;
u32 fpcr_mode = 0; u32 fpcr_mode = 0;
u32 FPSCR_nzcv = 0; u32 fpsr_nzcv = 0;
u32 old_FPSCR = 0; u32 old_FPSCR = 0;
u32 Fpscr() const; u32 Fpscr() const;
void SetFpscr(u32 FPSCR); void SetFpscr(u32 FPSCR);