mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
1473 commits 1 branch 0 tags 34 MiB
Commit graph

385 commits

Author SHA1 Message Date
Lioncash
4c3d7c5a8d A64: Implement FCVTL{2} 2020-04-22 20:53:45 +01:00
Lioncash
7eb6be7a6a A64: Implement FMAXNM and FMINNM vector variants. 
Currently we can implement these in terms of the scalar IR variants.
 2020-04-22 20:53:45 +01:00
Lioncash
8b65ea68c0 A64: Implement FMAXP, FMAXNMP, FMINP, and FMINNMP's vector variants 
We can just implement these in terms of scalars for the time being.
 2020-04-22 20:53:45 +01:00
MerryMage
8a3b6364c2 load_store_exclusive: Define s == t state to be Constraint_NONE 
Downstream (yuzu) mentioned that the instruction:

STXR W9, W9, [X0]

was executed in the program "Crash N-Sane Trilogy".
 2020-04-22 20:53:45 +01:00
MerryMage
cd40e4dae0 A64/translate: Allow for unpredictable behaviour to be defined 2020-04-22 20:53:45 +01:00
MerryMage
d1d6f4feb5 system: Implement MRS CNTFRQ_EL0 2020-04-22 20:53:45 +01:00
Lioncash
7ef7def661 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 
Currently we implement these in terms of the scalar variants. Falling
back to the interpreter is slow enough to make it more effective than
doing that.
 2020-04-22 20:46:23 +01:00
Lioncash
a4b0e2ace6 A64: Implement UQADD/UQSUB's scalar variants 2020-04-22 20:46:23 +01:00
MerryMage
f5e11d117a A64: Implement FMULX, scalar single/double variant 2020-04-22 20:46:23 +01:00
MerryMage
9669e49817 A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant 2020-04-22 20:46:23 +01:00
MerryMage
f2393488fe A64: Implement SQADD and SQSUB, scalar variant 2020-04-22 20:46:23 +01:00
Lioncash
d0fdd3c6e6 simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function 
Deduplicates a bit of code and makes its layout consistent with the
paired variants
 2020-04-22 20:46:23 +01:00
Lioncash
2bea2d0512 A64: Implement SMAXP, SMINP, UMAXP, UMINP 2020-04-22 20:46:23 +01:00
Lioncash
43344c5400 A64: Implement SMAXV, SMINV, UMAXV, and UMINV 2020-04-22 20:46:23 +01:00
Lioncash
7fdd8b0197 A64: Implement PMULL{2} 2020-04-22 20:46:23 +01:00
Lioncash
5ebf496d4e translate: Deduplicate GetDataSize() functions 
Avoids defining the same function multiple times in different files.
 2020-04-22 20:46:22 +01:00
Lioncash
f83cd2da9a floating_point_{conditional}_compare: Deduplicate code 
Deduplicates the implementation code of instructions by extracting the
code to a common function.
 2020-04-22 20:46:22 +01:00
Lioncash
b48fb8ca6b A64: Implement PMUL 2020-04-22 20:46:22 +01:00
MerryMage
dd4ac86f8e A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
28b38916a8 A64: Implement FCVTZS (vector, integer), single/double variant 2020-04-22 20:46:22 +01:00
Lioncash
c778c7b868 A64: Implement FMAX's vector single and double precision variants 2020-04-22 20:46:22 +01:00
Lioncash
009879d92b A64: Implement FMIN's vector single and double precision variants 2020-04-22 20:46:22 +01:00
MerryMage
10de36394e A64: Implement FRECPS, vector/scalar single/double variants 2020-04-22 20:46:22 +01:00
MerryMage
f66f61d8ab A64: Implement FRECPE, vector single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
27c73dd56a A64: Implement FRECPE, scalar single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
642b6c31d2 A64: Implement MLA, MLS (by element), vector single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
0de37b11ad A64: Implement FMLS (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
934132e0c5 A64: Implement FMLA (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
ecbf9dbae5 IR: Implement A64OrQC 2020-04-22 20:46:22 +01:00
MerryMage
f0fecf2615 A64: Implement UQSHRN, UQRSHRN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
8f4c1a8558 emit_x64_vector: -0x80000000 isn't -0x80000000 2020-04-22 20:46:22 +01:00
MerryMage
b455b566e7 A64: Implement UQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
3874cb37e3 A64: Implement SQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
712c6c1d7e A64: Implement SQSHRUN, SQRSHRUN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
c5722ec963 simd_shift_by_immediate: Simplify ShiftRight 2020-04-22 20:46:22 +01:00
MerryMage
f020dbe4ed A64: Implement SQXTUN 2020-04-22 20:46:22 +01:00
MerryMage
b2e4c16ef8 A64: Implement FRSQRTS (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
45dc5f74f3 A64: Implement FRSQRTE (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage
b74d5520f9 A64: Implement FRSQRTS (scalar), single/double variant 2020-04-22 20:46:22 +01:00
Lioncash
ace7d2ba50 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
Lioncash
49c7edf7c6 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant 2020-04-22 20:46:21 +01:00
Lioncash
c704acafe4 A64: Implement FMUL (by element)'s scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
Lioncash
b7bd70fd19 A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV 2020-04-22 20:46:21 +01:00
Lioncash
3447c82656 translate: Return by bool in helpers where applicable 
Gets rid of a bit of duplication regarding the early-out cases and makes
all helpers functions consistent (previously some had a return type of
bool, while others had a return type of void).
 2020-04-22 20:46:21 +01:00
MerryMage
f837ce8e78 simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant 2020-04-22 20:46:21 +01:00
MerryMage
16061c28f3 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant 2020-04-22 20:46:21 +01:00
MerryMage
55eaa16615 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT 
Discovered by @Subv.
Fixes incomplete fix begun in 5a91c94dca47c9702dee20fbd5ae1f4c07eef9df.
That fix fails to take into account that LinkBlock doesn't update ticks until there
are no remaining ticks to be executed.

Test added to confirm fix.
 2020-04-22 20:46:21 +01:00
Lioncash
e5d80e998e A64: Implement SADDLV 2020-04-22 20:46:21 +01:00
Lioncash
a1bc8ddb53 A64: Implement UADDLV 2020-04-22 20:46:21 +01:00
MerryMage
b53127600b fp: A64::FPCR -> FP::FPCR 2020-04-22 20:46:21 +01:00