Lioncash
35a29a9665
A64: Implement ZIP1
2020-04-22 20:46:13 +01:00
FernandoS27
586854117b
Implemented UMULH and SMULH instructions
2020-04-22 20:46:13 +01:00
MerryMage
aac5af50e2
IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
2020-04-22 20:46:13 +01:00
MerryMage
dd2a6684fe
IR: Add ConditionalSelectNZCV instruction
2020-04-22 20:46:13 +01:00
Lioncash
40614202e7
A64: Implement AESD
2020-04-22 20:46:13 +01:00
Lioncash
ccef85dbb7
A64: Implement AESE
2020-04-22 20:46:13 +01:00
MerryMage
8931ee346b
IR: Add IR instruction NZCVFromPackedFlags
...
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
2020-04-22 20:46:13 +01:00
MerryMage
ed2bedec43
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
2020-04-22 20:46:13 +01:00
MerryMage
ebfc51c609
IR: Implement VectorSetElement{8,16,32,64}
2020-04-22 20:46:13 +01:00
Lioncash
a5c4fbc783
A64: Implement AESIMC and AESMC
2020-04-22 20:46:13 +01:00
Lioncash
af1384d700
A64: Implement CRC32
2020-04-22 20:46:12 +01:00
MerryMage
f023bbb893
A32: Add ExceptionRaised IR instruction and use it
2020-04-22 20:46:12 +01:00
Lioncash
7ffbebf290
A64: Implement CRC32C
2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050
A64: Implement EXTR
2020-04-22 20:46:12 +01:00
MerryMage
b513b2ef05
IR: Implement IR instructions A64{Get,Set}S
2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions ( #142 )
2020-04-22 20:44:38 +01:00
MerryMage
285fd22c30
IR: Add IR instruction VectorZeroUpper
2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806
Implemented SDIV and UDIV instructions
2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621
IR: Add IR instructions A64Memory{Read,Write}128
...
This implementation only works on macOS and Linux.
2020-04-22 20:44:37 +01:00
MerryMage
e00a522cba
IR: Add IR instruction VectorGetElement{8,16,32,64}
2020-04-22 20:44:37 +01:00
MerryMage
28ccd85e5c
IR: Add IR instruction ZeroExtendToQuad
2020-04-22 20:44:37 +01:00
MerryMage
793753bf63
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
2020-04-22 20:44:37 +01:00
MerryMage
eaf545877a
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
2020-04-22 20:42:46 +01:00
Lioncash
b612782445
opcodes: Add 64-bit CountLeadingZeroes opcode
2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536
A64: Implement AND (vector)
2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b
A64: Implement ADD (vector, vector)
2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf
IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
...
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2020-04-22 20:42:46 +01:00
MerryMage
6395f09f94
IR: Implement Conditional Select
2020-04-22 20:42:45 +01:00
MerryMage
0992987c98
A64: Add ExceptionRaised IR instruction
...
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
2020-04-22 20:42:45 +01:00
MerryMage
25411da838
A32: Implement load stores (immediate)
2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05
A64: Implement SVC
2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48
A64: Implement compare and branch
2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3
A64: Implement branch (register)
2020-04-22 20:42:45 +01:00
MerryMage
0641445e51
A64: Implement logical
2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97
A64: Implement addsub instructions
2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0
A64: Implement ADD_shifted
2020-04-22 20:42:44 +01:00
MerryMage
44f7f04b5c
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2020-04-22 20:39:27 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
19a7fb8992
jit_state: Split off CPSR.NZCV
2020-04-22 20:26:40 +01:00
MerryMage
d1e0a29cd9
Implement IR instruction PackedSelect, reimplement SEL
2020-04-22 20:26:07 +01:00
MerryMage
05e97058c3
parallel: Add and Subtract with Exchange improvements
...
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
MerryMage
bbeea72eba
ir_opt: Remove redundant shift instructions
2017-02-26 15:28:14 +00:00
MerryMage
48693eb6ff
Implement coprocessor-related microinstructions
...
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d
IR: Remove unused microinstructions NegateLowWord and NegateHighWord
2017-01-05 20:16:39 +00:00
FernandoS27
d5610eb26c
Implement UHASX, UHSAX, SHASX and SHSAX ( #75 )
2016-12-28 21:32:22 +00:00
Fernando Sahmkow
677f62dd6f
Implement SHSUB8 and SHSUB16 ( #74 )
...
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
2016-12-22 12:02:24 +00:00
MerryMage
6a269a6ebd
IR: Add microinstructions UnsignedSaturation and SignedSaturation
2016-12-21 19:51:25 +00:00
FernandoS27
8919265d2c
Implement SADD8, SADD16, SSUB8, SSUB16, USUB16
2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245
Implemented USAD8 and USADA8
2016-12-20 21:52:38 +00:00
MerryMage
96e46ba6b5
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:34:29 +00:00
MerryMage
52e1445f43
Implement USUB8
2016-12-05 00:29:15 +00:00
MerryMage
5c1aab1666
Implement CLZ
...
Includes tests
2016-12-04 22:56:33 +00:00
MerryMage
1a1646d962
Implement UADD8
2016-12-04 20:52:33 +00:00
MerryMage
7cad6949e7
IR: Implement new pseudo-operation GetGEFromOp
2016-12-04 20:52:06 +00:00
MerryMage
e166965f3e
Implement VCMP
2016-12-03 11:41:09 +00:00
Merry
0ff8c375af
Implement UHSUB8 and UHSUB16 ( #48 )
2016-11-26 18:27:21 +00:00
Merry
cb17f9a3ed
Implement SHADD8 and SHADD16 ( #47 )
2016-11-26 18:12:29 +00:00
MerryMage
c0c1bb1094
Implemented UHADD16
2016-11-26 11:28:20 +00:00
Sebastian Valle
4d44474ad4
Implemented the ARM UHADD8 instruction. ( #45 )
...
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
2016-11-25 20:32:22 +00:00
MerryMage
b6f7b8babd
ir: Implement GetGEFlags, SetGEFlags
2016-11-23 19:44:27 +00:00
MerryMage
dca3b2f079
Implement VMRS and VMSR
2016-08-26 22:47:54 +01:00
MerryMage
b5a86889cd
Implement VCVT
2016-08-23 22:20:04 +01:00
MerryMage
e164ede4dc
TranslateArm: Implement MRS, MSR (imm), MSR (reg)
2016-08-15 11:50:49 +01:00
MerryMage
960d14d18e
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032
TranslateArm: Implement QADD8 and UQADD8.
2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb
TranslateArm: Implement QSUB8.
2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2
TranslateArm: Implement UQSUB8.
2016-08-12 19:00:44 +01:00
MerryMage
df39308e03
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:57:20 +01:00
Tillmann Karras
5d26899ac9
Add simplified LogicalShiftRight64 IR opcode
2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5
Add support for the APSR.Q flag
2016-08-08 22:27:04 +01:00
MerryMage
a2c2db277b
VFP: Implement VMOV (all variants)
2016-08-07 19:25:12 +01:00
MerryMage
0f412247ed
VFP: Implement VSQRT
2016-08-07 12:19:07 +01:00
MerryMage
3f1345a1a5
VFP: Implement VNMUL, VDIV
2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359
VFP: Implement VMUL
2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f
VFP: Implement VSUB
2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210
VFP: Implement VABS
2016-08-07 01:27:18 +01:00
Tillmann Karras
846d07d7b5
Add Sub64 opcode
2016-08-06 21:17:11 +01:00
MerryMage
4b31ea25a7
VFP: Implement VADD.{F32,F64}
2016-08-06 20:03:15 +01:00
MerryMage
640ce48baa
VFP: Implement {Get,Set}ExtendedRegister{32,64}
2016-08-05 19:06:10 +01:00
MerryMage
b4aa01ccf4
Merge remote-tracking branch 'tilkax/master'
2016-08-05 14:14:06 +01:00
MerryMage
ca40015145
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
2016-08-05 14:07:27 +01:00
Tillmann Karras
3fdc093d10
Add more IR opcodes for multiply instructions
...
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-05 02:09:30 +01:00
Tillmann Karras
2488926341
Add IR opcode RotateRightExtended
...
to rotate through the carry flag
2016-08-03 00:47:16 +01:00
MerryMage
be87038ffd
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
MerryMage
51448aa06d
More Speed
2016-07-22 23:55:00 +01:00
MerryMage
90d317b868
Implement memory endianness. Implement Thumb SETEND instruction.
2016-07-20 15:34:17 +01:00
MerryMage
3720da4e19
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +01:00
MerryMage
9b2aff166a
Implement arm_SVC
2016-07-14 14:29:46 +01:00
MerryMage
09420d190b
IR: Implement IR microinstructions ALUWritePC and LoadWritePC
2016-07-12 10:58:14 +01:00
MerryMage
1410221b47
Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
2016-07-11 23:11:05 +01:00
MerryMage
e7922e4fef
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +01:00
MerryMage
d11df9067d
Implement thumb1_BIC_reg
2016-07-10 10:44:45 +08:00
MerryMage
98a64a92b1
Implement thumb1_ORR_reg
2016-07-10 09:06:38 +08:00
MerryMage
8145b33882
Implemented thumb1_ROR_reg
2016-07-10 08:18:17 +08:00
MerryMage
92142d5a22
Implement thumb1_SUB_reg
2016-07-08 18:49:30 +08:00
MerryMage
df0c324923
Implement thumb1_EOR_reg
2016-07-08 18:14:54 +08:00
MerryMage
8a0511d297
Implement thumb1_AND_reg
2016-07-08 17:44:53 +08:00
MerryMage
d0b48bfb59
Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
2016-07-08 17:44:51 +08:00
