MerryMage
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642b6c31d2
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A64: Implement MLA, MLS (by element), vector single/double variant
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
0de37b11ad
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A64: Implement FMLS (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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64c2f698a2
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emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly
MSVC doesn't like dealing with auto return types
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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2ef59b4f03
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emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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04f325a05e
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IR: Implement FPVectorNeg
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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934132e0c5
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A64: Implement FMLA (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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771a4fc20b
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IR: Implement FPVectorMulAdd
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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3218bb9890
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emit_x64_vector_floating_point: Standardize naming scheme
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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8f72be0a02
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emit_x64_floating_point: Simplify indexers
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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25b28bb234
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emit_x64_vector_floating_point: Simplify EmitVectorOperation*
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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1edd0125b2
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mp: rename mp.h to mp/function_info.h
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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0921678edb
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emit_x64_vector: Slightly improve ArithmeticShiftRightByte
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
43407c4bb4
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emit_x64_vector: Simplify VectorShuffleImpl
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
ecbf9dbae5
|
IR: Implement A64OrQC
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
f0fecf2615
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A64: Implement UQSHRN, UQRSHRN (vector)
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
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8f4c1a8558
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emit_x64_vector: -0x80000000 isn't -0x80000000
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b455b566e7
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A64: Implement UQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
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MerryMage
|
e686a81612
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emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison
Allows non-SSE4.1 to produce the correct FPSR.QC flag
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
3874cb37e3
|
A64: Implement SQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
8ef114d48f
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emit_x64_vector: packusdw reqiures SSE4.1
In EmitVectorSignedSaturatedNarrowToUnsigned32.
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
712c6c1d7e
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A64: Implement SQSHRUN, SQRSHRUN (vector)
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
c5722ec963
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simd_shift_by_immediate: Simplify ShiftRight
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
f020dbe4ed
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A64: Implement SQXTUN
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2020-04-22 20:46:22 +01:00 |
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MerryMage
|
6918ef7360
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microinstruction: Reorganize FPSCR related instruction queries
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2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
a639fa5534
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microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
These were forgotten when the opcodes were added.
|
2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
3ca18d8a6d
|
u128: Make Bit() a const-qualified member function
This function doesn't modify the struct members, so it can be made
const.
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b2e4c16ef8
|
A64: Implement FRSQRTS (vector), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
45dc5f74f3
|
A64: Implement FRSQRTE (vector), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b74d5520f9
|
A64: Implement FRSQRTS (scalar), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
506e544bfe
|
IR: Implement FPRSqrtStepFused
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
6eb069e80d
|
fp: Implement FPRSqrtStepFused
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b0ff35fcd1
|
fp: Implement FPNeg
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
ca6774ccce
|
process_nan: Add two operand variant
|
2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
ace7d2ba50
|
A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
66bb05fc0a
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emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation
|
2020-04-22 20:46:21 +01:00 |
|
Lioncash
|
070637e0f6
|
fp: Use a forward declaration in fused.h
It's permissible to forward declare here, so we can do so and eliminate
a direct header dependency
|
2020-04-22 20:46:21 +01:00 |
|
Lioncash
|
030820f649
|
u128: Implement comparison operators in terms of one another
We can just implement the comparisons in terms of operator< and
implement inequality with the negation of operator==.
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
a04553eb91
|
tests: Print cpu info
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
76b07d6646
|
u128: StickyLogicalShiftRight requires special-casing for amount == 64
In this case (128 - amount) == 64, and this invokes undefined behaviour
|
2020-04-22 20:46:21 +01:00 |
|
Lioncash
|
49c7edf7c6
|
A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant
|
2020-04-22 20:46:21 +01:00 |
|
Lioncash
|
c704acafe4
|
A64: Implement FMUL (by element)'s scalar double/single-precision variant
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
0ce11b7b15
|
emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64}
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
e199887fbc
|
fp: Implement FPMulAdd
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
53a8c15d12
|
process_nan: Add FPProcessNaNs3
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
1c8e93e74d
|
block_of_code: Add SysV ABI fifth and sixth parameters
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
1fe8f51c54
|
u128: Add StickyLogicalShiftRight
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
b0afd53ea7
|
u128: Add Multiply64To128
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
5566fab29a
|
u128: Add u128::Bit
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
3e62fea003
|
u128: Add comparison operators
|
2020-04-22 20:46:21 +01:00 |
|
MerryMage
|
f17cd6f2c5
|
unpacked: Use ResidualErrorOnRightShift in FPRoundBase
Fixes a bug relating to exponents that are severely out of range.
|
2020-04-22 20:46:21 +01:00 |
|