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421 commits

Author SHA1 Message Date
emuplz
8728444af8 added support for instruction ic ivau 2021-02-17 20:38:06 +00:00
MerryMage
62003a2d89 A32/ir_emitter: Implement UpdateUpperLocationDescriptor 2021-02-07 20:41:48 +00:00
Lioncash
0e1112b7df Revert "basic_block: Mark move constructor and assignment as noexcept" 
This reverts commit 4f12e86ebb.

Big fan of MSVC preventing standard behavior.
 2020-08-14 16:49:40 -04:00
Lioncash
4f12e86ebb basic_block: Mark move constructor and assignment as noexcept 
Allows the type to play nicely with standard library facilities better
(also we shouldn't be throwing in move operations to begin with).
 2020-08-14 14:38:28 -04:00
MerryMage
f35aaa017c IR: Add VectorDeinterleave{Even,Odd}Lower 2020-07-04 11:04:10 +01:00
MerryMage
3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) 2020-06-22 22:08:58 +01:00
MerryMage
43a4b2a0b8 ir_emitter: Remove dummy fpcr_controlled arguments from scalar FP instructions 2020-06-21 14:28:25 +01:00
MerryMage
c836b389c8 emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions 2020-06-21 14:28:25 +01:00
MerryMage
7d1e103ff5 IR: Implement VectorTranspose 2020-06-21 12:14:13 +01:00
MerryMage
8bbc9fdbb6 A32: Implement ASIMD VTBX 2020-06-20 22:35:31 +01:00
MerryMage
92cb4a5a34 A32: Implement ASIMD VRSQRTE 2020-06-20 15:13:22 +01:00
MerryMage
6f59c2cd8e A32: Implement ASIMD VRECPE 2020-06-20 15:07:06 +01:00
MerryMage
d3dc50d718 A32: Implement ASIMD VRSQRTS 2020-06-20 15:06:06 +01:00
MerryMage
8f506c80c3 A32: Implement ASIMD VRECPS 2020-06-20 14:39:05 +01:00
MerryMage
f58e247ef3 A32: Implement ASIMD VPADD (floating-point) 2020-06-20 14:25:04 +01:00
MerryMage
e006f0a205 A32: Implement ASIMD VSUB (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage
4c939b9d0a A32: Implement ASIMD VADD (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage
5ec8e48593 A32: Implement ASIMD VMUL (floating-point) 
* Also add fpcr_controlled arguments to FPVectorMul IR instruction
* Merge ASIMD floating-point instruction implementations
 2020-06-20 14:20:28 +01:00
MerryMage
bb4f3aa407 A32: Implement ASIMD VMAX, VMIN (floating-point) 2020-06-20 03:21:07 +01:00
MerryMage
656419286c ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual} 2020-06-20 00:50:40 +01:00
MerryMage
d3664b03fe ir_emitter: Default fpcr_controlled arguments to true 2020-06-19 22:51:23 +01:00
MerryMage
2c1a4843ad A32 global exlcusive monitor 2020-06-16 17:54:21 +01:00
MerryMage
7ea521b8bf a32_emit_x64: Change ExclusiveWriteMemory64 to require a single U64 argument 2020-06-16 13:32:50 +01:00
MerryMage
f3845cea9a A32: Implement ASIMD VQSUB instruction 2020-05-30 18:19:17 +01:00
MerryMage
4e90754873 IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub} 2020-05-30 15:55:32 +01:00
MerryMage
ebddf6cca0 basic_block: Allow printing of invalid instruction pointers 2020-05-28 20:39:50 +01:00
MerryMage
07108246cf A32/IR: Add SetVector and GetVector 2020-05-28 20:39:19 +01:00
MerryMage
c59a127e86 opcodes: Switch from std::map to std::array 
Optimization.
 2020-05-17 17:01:39 +01:00
MerryMage
d0b45f6150 A32: Implement ARMv8 VST{1-4} (multiple) 2020-05-17 17:01:39 +01:00
Fernando Sahmkow
97b9d3e058 Exclusive Monitor: Rework exclusive monitor interface. 2020-05-03 01:40:37 +01:00
MerryMage
5c0bb5cc63 Remove unreachable code (MSVC warnings) 2020-04-23 16:36:34 +01:00
MerryMage
a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage
4573511fe3 constant_propagation_pass: Prepare for IR matchers 2020-04-22 21:07:09 +01:00
MerryMage
0d7476d3ec constant_propagation_pass: Propagate constants across commutative operations 
e.g. (a & b) & c == a & (b & c) where b and c are constants
 2020-04-22 21:07:09 +01:00
MerryMage
f59b9fb020 IR: Add ReplicateBit microinstruction 2020-04-22 21:07:09 +01:00
MerryMage
93adcfa5c6 value: Add GetInstRecursive 2020-04-22 21:06:18 +01:00
MerryMage
2ae68b13ed value: Add IsIdentity function 2020-04-22 21:06:18 +01:00
MerryMage
4636055646 a32_emit_x64: Implement fastmem 2020-04-22 21:06:17 +01:00
MerryMage
09d3c77d74 IR: Add masked shift IR instructions 
Also use these in the A64 frontend to avoid the need to mask the shift amount.
 2020-04-22 21:06:17 +01:00
MerryMage
e10985d179 ir/basic_block: Add FastDispatchHint to TerminalToString 
Use a boost::static_visitor to ensure this is caught at compile-time in the future.
 2020-04-22 21:04:23 +01:00
Lioncash
af3614553b A64/impl: Move AccType and MemOp enum into general IR emitter header 
These will be used by both frontends in the future, so this performs the
migratory changes separate from the changes that will make use of them.
 2020-04-22 21:04:23 +01:00
Merry
1c97edac77 Merge pull request #503 from lioncash/cmp 
A64: Implement half-precision variants of FCMEQ
 2020-04-22 21:04:22 +01:00
Merry
f252a62c1b Merge pull request #502 from lioncash/header 
General: Remove unnecessary includes
 2020-04-22 21:04:22 +01:00
Lioncash
349d4b577a General: Remove unnecessary includes 
Removes unnecessary header dependencies that have accumulated over time
as changes have been made. Lessens the amount of files that need to be
rebuilt when the headers change.
 2020-04-22 21:04:22 +01:00
Lioncash
43fd2b400a frontend/ir_emitter: Add half-precision opcode for FPVectorEquals 2020-04-22 21:04:22 +01:00
Lioncash
6b9bf7868a General: Correct typos is code comments 2020-04-22 21:04:22 +01:00
Lioncash
b79ce71b0f ir/basic_block: std::move Terminal within SetTerminal and ReplaceTerminal 
A terminal isn't a trivial type (and boost::variant is allowed to heap
allocate), so we can std::move it here to avoid a redundant copy.
 2020-04-22 21:04:22 +01:00
Lioncash
63eff4e7cc ir/terminal: std::move constructor parameters where applicable 
Allows the compiler to choose the most suitable code in this scenario,
given a Terminal isn't a trivial type.
 2020-04-22 21:04:22 +01:00
Lioncash
bd755ae494 frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit 
This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
 2020-04-22 21:02:47 +01:00
Lioncash
c6f99235e1 frontend/ir/ir_emitter: Remove unnecessary logical shift overloads 
These aren't necessary anymore, now that the U32U64 overload already
exists.
 2020-04-22 21:02:46 +01:00