MerryMage
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99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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429dc24587
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IR: Merge U32 and U64 variants of FP instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ed2bedec43
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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6414736a8d
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emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ebfc51c609
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IR: Implement VectorSetElement{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a5c4fbc783
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A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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744495e23d
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iterator_util: Make Reverse constexpr
C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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ab9b5fb8aa
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Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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af1384d700
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A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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64761dbc72
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scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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bafb39ebc5
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A64: Add Disassemble method
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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cc0eb18a0b
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A32: data_processing: Remove !S assertions
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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865a30eb0d
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A32: Implement BKPT
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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f023bbb893
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A32: Add ExceptionRaised IR instruction and use it
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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7ffbebf290
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A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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d7044bc751
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assert: Use fmt in ASSERT_MSG
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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52268298a8
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a64_emit_x64: Perform RSB predictions
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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98ec9c5f90
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A32: Change UserCallbacks to be similar to A64's interface
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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b9ce660113
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reg_alloc: std::move RegAlloc's function argument
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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ed561d6653
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General: Add missing override specifiers
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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b2d99eddc6
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EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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f4f774f9f6
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a64_get_set_elimination_pass: Simplify algorithm
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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54de64f5bf
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a64_emit_x64: bug: x64 sign-extends 32-bit immediates
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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6fc228f7fd
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ir_opt: Add A64 Get/Set Elimination Pass
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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e01b500aea
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ir_emitter: Allow the insertion point for new instructions to be set
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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af793c2527
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{a32,a64}_interface: Predict entrypoint
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2020-04-22 20:46:12 +01:00 |
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Lioncash
|
7734cf1050
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A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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88ae7fce52
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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d497464c9f
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a64_jitstate: Have 128-bit wide spills
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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b513b2ef05
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IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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16fa2cd8f6
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a64_emit_x64: Use xword from Xbyak::util
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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7abd673a49
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A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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ba3d6da0c8
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load_store_register_unprivileged: bug: LDTRSW
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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75756137c6
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A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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d5283e46e8
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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4ce9c65cfb
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reg_alloc: Use std::exchange
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2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
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e0c12ec2ad
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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94383fd934
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microinstruction: Missed A64{Read,Write}Memory128 from opcode information
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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d124a1d761
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emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable
For CPUs that didn't support SSE4.1, this was a bug.
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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589ad7232f
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Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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ae880d8391
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A64: Fix bugs and address review comments
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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3aeb7ca50c
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Add missing returns
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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41e6e659c5
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A64: Implement Load/Store register (unprivileged)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
01a26fa644
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fixup: travis: Test with disabled CPU feature detection
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2020-04-22 20:44:37 +01:00 |
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Lioncash
|
5281d3c6d5
|
CMakeLists: Add opcodes.inc to the source file list
Allows the file to show up nicely within IDEs
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2020-04-22 20:44:37 +01:00 |
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MerryMage
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30936f5e94
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travis: Test with disabled CPU feature detection
Ensure that fallbacks are working correctly.
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
285fd22c30
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IR: Add IR instruction VectorZeroUpper
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
da3e9a5704
|
a64_emit_x64: bug: EmitA64WriteMemory128 should write not read
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2020-04-22 20:44:37 +01:00 |
|
FernandoS27
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ab84524806
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Implemented SDIV and UDIV instructions
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2020-04-22 20:44:37 +01:00 |
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