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Author SHA1 Message Date
ascpixi
9d45823399 Replace some more dead repo references 2024-03-05 17:24:40 +01:00
ascpixi
58a81a9bdd Use yuzu-mirror copies for MerryMage repos 
These repositories, unfortunately, do not exist anymore.
 2024-03-05 17:10:08 +01:00
Merry
a41c380246 backend/rv64: Add stub implementations for FPMulSub 2024-03-03 00:18:00 +00:00
Yang Liu
8a11790363 backend/rv64: Implement basic Add32 2024-03-02 19:38:46 +00:00
Yang Liu
6142db8647 backend/rv64: Implement GetCFlagFromNZCV 2024-03-02 19:38:46 +00:00
Yang Liu
483dcba9b6 backend/rv64: Implement basic LogicalShiftRight32 2024-03-02 19:38:46 +00:00
Yang Liu
02d8a7ff10 backend/rv64: Stub all IR instruction implementations 2024-03-02 19:38:46 +00:00
Yang Liu
e7bafeae24 mcl: Add UNIMPLEMENTED macro 2024-03-02 19:38:46 +00:00
Yang Liu
208acb3026 backend/rv64: Implement A32SetCpsrNZCV 2024-03-02 19:38:46 +00:00
Yang Liu
09c6f22da9 backend/rv64: Implement GetNZCVFromOp 2024-03-02 19:38:46 +00:00
Yang Liu
f6e02048f5 backend/rv64: Implement basic Sub32 2024-03-02 19:38:46 +00:00
Yang Liu
b485553ed8 backend/rv64: Implement Identity 2024-03-02 19:38:46 +00:00
Yang Liu
1de237bf24 backend/rv64: Initial implementation of terminals 2024-03-02 19:38:46 +00:00
Yang Liu
672d43fbb7 backend/rv64: Add StackLayout to stack 2024-03-02 19:38:46 +00:00
Yang Liu
3ff8b9d346 backend/rv64: Implement UpdateAllUses 2024-03-02 19:38:46 +00:00
Yang Liu
cc2a6fd6fb backend/rv64: Implement AssertNoMoreUses and some minor tweaks 2024-03-02 19:38:46 +00:00
Yang Liu
b7cca7c53d backend/rv64: Use biscuit LI() 2024-03-02 19:38:46 +00:00
Yang Liu
f856ac9f33 backend/rv64: Add minimal toy implementation enough to execute LSLS 2024-03-02 19:38:46 +00:00
Yang Liu
62ff78d527 backend/rv64: Initial implementation of register allocator 2024-03-02 19:38:46 +00:00
Yang Liu
c47dacb1de backend/rv64: Adjust how relocations are stored 2024-03-02 19:38:46 +00:00
Yang Liu
c90c4d48d2 backend/rv64: Rework on pointer types 2024-03-02 19:38:46 +00:00
Yang Liu
d743fe8a2a backend/rv64: Add a dummy code generation 2024-03-02 19:38:46 +00:00
Yang Liu
4324b262aa backend/rv64: Add biscuit as the assembler 2024-03-02 19:38:46 +00:00
Yang Liu
a4b9b431b0 backend/rv64: Add initial RISC-V framework 
RISC-V target is now compilable.
 2024-03-02 19:38:46 +00:00
Yang Liu
add5238180 github: Add basic RISC-V CI 2024-03-02 19:38:46 +00:00
Merry
8125738fa2 externals: Add biscuit 
Merge commit 'e4a733d5b2e02e7095847892f29ed8288d55d91e' as 'externals/biscuit'
 2024-03-02 19:36:30 +00:00
Merry
e4a733d5b2 Squashed 'externals/biscuit/' content from commit 1d53c9e6 
git-subtree-dir: externals/biscuit
git-subtree-split: 1d53c9e6cfe56544982200a5bac15a5de064936b
 2024-03-02 19:36:24 +00:00
Merry
fa6cc2e4b2 dynarmic: 6.7.0 2024-03-02 17:07:42 +00:00
Ash
732a657694 Change Config to make fastmem_pointer of zero valid. 
This changes Dynarmic::A32/A64::Config to store fastmem_pointer in
a std::optional<uintptr_t>, allowing the user to pass a zero base
address for the guest memory, which can be used to effectively
implement a shared address space between the host and the guest.
 2024-03-02 16:31:20 +00:00
zmt00
f884bc0dfc emit_x64_vector: Implement AVX2 AVShift64 2024-02-24 17:08:27 +00:00
zmt00
879142d424 emit_x64_vector: Refactor AVX2 AVShift32, LVShift{32,64} 2024-02-24 17:08:27 +00:00
zmt00
043f21df7d tests/A64: Update {S,U}SHL tests 
Converted tests to use oaknut, and added some extra test cases. SSHL's
additional tests are targetd to make sure that the sign of the lowest
byte is used to determine shift direction, not the entire element. USHL
targets this as well as just having more negative (right shift) cases in
general.
 2024-02-24 17:08:27 +00:00
zmt00
2c0dc88715 emit_x64_vector: Implement AVX2 UnsignedRoundingShiftLeft{32,64} 2024-02-20 14:16:15 +00:00
zmt00
ef4f79811b tests/A64: Add URSHL tests 2024-02-20 14:16:15 +00:00
zmt00
4f08226e0e emit_x64_vector: Refactor pre-SSE4.1 min/max instruction replacements 2024-02-17 13:17:01 +00:00
zmt00
60a6092b65 tests/A64: Add non-paired min/max integer tests 2024-02-17 13:17:01 +00:00
zmt00
0adc972cd9 emit_x64_vector: Optimize VectorSignedSaturatedAbs 2024-02-13 18:46:42 +00:00
zmt00
cc9f00645d tests/A64: Add SQABS tests 2024-02-13 18:46:42 +00:00
Merry
69dc836977 backend/arm64: A64: Implement DumpDisassembly 2024-02-13 02:21:22 +00:00
Merry
4ae4750b5a emit_arm64_a64: Take into account currently loaded FPSR 
Previously we just retrieved the last stored FPSR and used that when the guest asks for the current FPSR.
This is incorrect behaviour. We failed to take into account the current state of the host FPSR.

Here we take this into account. This bug was discovered via #795.
 2024-02-13 02:19:55 +00:00
Merry
ba8192d890 dynarmic: 6.6.3 2024-02-10 19:34:16 +00:00
Merry
ee84ec0bb9 backend/x64: Reduce races on invalidation requests in interface 
This situation occurs when RequestCacheInvalidation is called from
multiple threads. This results in unusual issues around memory
allocation which arise from concurrent access to invalid_cache_ranges.

There are several reasons for this:
1. No locking around the invalidation queue.
2. is_executing is not multithread safe.

So here we reduce any cache clear or any invalidation to raise a
CacheInvalidation halt, which we execute immediately before or
immediately after Run() instead.
 2024-02-10 19:31:07 +00:00
Wunkolo
6d0995c948 tests/A64: Add negative-shift elements to USHL 2024-02-10 11:38:17 +00:00
Wunkolo
18717d216c emit_x64_vector: AVX512+GNFI implementation of EmitVectorLogicalVShift8 2024-02-10 11:38:17 +00:00
zmt00
f5df599e9d tests/A64: Convert recent tests to oaknut 2024-02-10 11:32:07 +00:00
zmt00
0785a6d027 ir: Implement FPMulSub 2024-02-10 11:31:54 +00:00
Wunkolo
a32e6f52ef tests/A64: Use oaknut for CLZ assembly 2024-02-06 18:15:34 +00:00
Wunkolo
eb5eb9cdf7 emit_x64_vector: GNFI implementation of EmitVectorCountLeadingZeros8 2024-02-06 18:15:34 +00:00
Wunkolo
1e5e7a7ae6 tests/A64: Add CLZ vector unit-tests 2024-02-06 18:15:34 +00:00
Merry
75235ffedb emit_x64_data_processing: Exclude edge case from lea path in EmitSub 
-0xffff'ffff'8000'0000 = 0x0000'0000'8000'0000 which is not a representable displacement
 2024-01-31 01:41:25 +00:00