MerryMage
|
28b38916a8
|
A64: Implement FCVTZS (vector, integer), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
507bcd8b8b
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IR: Implement FPVectorTo{Signed,Unsigned}Fixed
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
8f75a1fe04
|
fp/info: Replace constant value generators with FPValue
Instead of having multiple different functions we can just have one.
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
da261772ea
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emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min}
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
a0d6f0de57
|
emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs
|
2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
c778c7b868
|
A64: Implement FMAX's vector single and double precision variants
|
2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
009879d92b
|
A64: Implement FMIN's vector single and double precision variants
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
7b03da86c2
|
IR: Implement FPVector{Max,Min}
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
e76e1186bb
|
FPRecipEstimate: Move offset out of function
MSVC has weird lambda capturing rules.
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
ddcff86f9c
|
microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
10de36394e
|
A64: Implement FRECPS, vector/scalar single/double variants
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
901bd9b4e2
|
IR: Implement FPRecipStepFused, FPVectorRecipStepFused
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
f66f61d8ab
|
A64: Implement FRECPE, vector single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
939f5f5c7a
|
IR: Implement FPVectorRecipEstimate
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
27c73dd56a
|
A64: Implement FRECPE, scalar single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
fc2d33ae7b
|
IR: Implement FPRecipEstimate
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
c1dcfe29f7
|
IR: Implement FPRecipEstimate
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
7a673a8a43
|
fp: Change FPUnpacked to a normalized representation
Having a known position for the highest set bit makes writing algorithms easier
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
680395a803
|
fuzz_with_unicorn: Disable testing of FDIV
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
3fe45c6d8e
|
block_of_code: Add ABI_PARAMS array
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
642b6c31d2
|
A64: Implement MLA, MLS (by element), vector single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
0de37b11ad
|
A64: Implement FMLS (vector), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
64c2f698a2
|
emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly
MSVC doesn't like dealing with auto return types
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
2ef59b4f03
|
emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
04f325a05e
|
IR: Implement FPVectorNeg
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
934132e0c5
|
A64: Implement FMLA (vector), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
771a4fc20b
|
IR: Implement FPVectorMulAdd
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
3218bb9890
|
emit_x64_vector_floating_point: Standardize naming scheme
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
8f72be0a02
|
emit_x64_floating_point: Simplify indexers
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
25b28bb234
|
emit_x64_vector_floating_point: Simplify EmitVectorOperation*
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
1edd0125b2
|
mp: rename mp.h to mp/function_info.h
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
0921678edb
|
emit_x64_vector: Slightly improve ArithmeticShiftRightByte
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
43407c4bb4
|
emit_x64_vector: Simplify VectorShuffleImpl
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
ecbf9dbae5
|
IR: Implement A64OrQC
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
f0fecf2615
|
A64: Implement UQSHRN, UQRSHRN (vector)
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
8f4c1a8558
|
emit_x64_vector: -0x80000000 isn't -0x80000000
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b455b566e7
|
A64: Implement UQXTN (vector)
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
e686a81612
|
emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison
Allows non-SSE4.1 to produce the correct FPSR.QC flag
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
3874cb37e3
|
A64: Implement SQXTN (vector)
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
8ef114d48f
|
emit_x64_vector: packusdw reqiures SSE4.1
In EmitVectorSignedSaturatedNarrowToUnsigned32.
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
712c6c1d7e
|
A64: Implement SQSHRUN, SQRSHRUN (vector)
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
c5722ec963
|
simd_shift_by_immediate: Simplify ShiftRight
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
f020dbe4ed
|
A64: Implement SQXTUN
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
6918ef7360
|
microinstruction: Reorganize FPSCR related instruction queries
|
2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
a639fa5534
|
microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
These were forgotten when the opcodes were added.
|
2020-04-22 20:46:22 +01:00 |
|
Lioncash
|
3ca18d8a6d
|
u128: Make Bit() a const-qualified member function
This function doesn't modify the struct members, so it can be made
const.
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b2e4c16ef8
|
A64: Implement FRSQRTS (vector), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
45dc5f74f3
|
A64: Implement FRSQRTE (vector), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b74d5520f9
|
A64: Implement FRSQRTS (scalar), single/double variant
|
2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
506e544bfe
|
IR: Implement FPRSqrtStepFused
|
2020-04-22 20:46:22 +01:00 |
|