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249 commits

Author SHA1 Message Date
MerryMage
3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) 2020-06-22 22:08:58 +01:00
MerryMage
43a4b2a0b8 ir_emitter: Remove dummy fpcr_controlled arguments from scalar FP instructions 2020-06-21 14:28:25 +01:00
MerryMage
c836b389c8 emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions 2020-06-21 14:28:25 +01:00
MerryMage
7d1e103ff5 IR: Implement VectorTranspose 2020-06-21 12:14:13 +01:00
MerryMage
8bbc9fdbb6 A32: Implement ASIMD VTBX 2020-06-20 22:35:31 +01:00
MerryMage
92cb4a5a34 A32: Implement ASIMD VRSQRTE 2020-06-20 15:13:22 +01:00
MerryMage
6f59c2cd8e A32: Implement ASIMD VRECPE 2020-06-20 15:07:06 +01:00
MerryMage
d3dc50d718 A32: Implement ASIMD VRSQRTS 2020-06-20 15:06:06 +01:00
MerryMage
8f506c80c3 A32: Implement ASIMD VRECPS 2020-06-20 14:39:05 +01:00
MerryMage
f58e247ef3 A32: Implement ASIMD VPADD (floating-point) 2020-06-20 14:25:04 +01:00
MerryMage
e006f0a205 A32: Implement ASIMD VSUB (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage
4c939b9d0a A32: Implement ASIMD VADD (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage
5ec8e48593 A32: Implement ASIMD VMUL (floating-point) 
* Also add fpcr_controlled arguments to FPVectorMul IR instruction
* Merge ASIMD floating-point instruction implementations
 2020-06-20 14:20:28 +01:00
MerryMage
bb4f3aa407 A32: Implement ASIMD VMAX, VMIN (floating-point) 2020-06-20 03:21:07 +01:00
MerryMage
656419286c ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual} 2020-06-20 00:50:40 +01:00
MerryMage
d3664b03fe ir_emitter: Default fpcr_controlled arguments to true 2020-06-19 22:51:23 +01:00
MerryMage
f3845cea9a A32: Implement ASIMD VQSUB instruction 2020-05-30 18:19:17 +01:00
MerryMage
4e90754873 IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub} 2020-05-30 15:55:32 +01:00
MerryMage
d0b45f6150 A32: Implement ARMv8 VST{1-4} (multiple) 2020-05-17 17:01:39 +01:00
MerryMage
a8a712c801 Relicense to 0BSD 2020-04-23 15:45:57 +01:00
MerryMage
4573511fe3 constant_propagation_pass: Prepare for IR matchers 2020-04-22 21:07:09 +01:00
MerryMage
f59b9fb020 IR: Add ReplicateBit microinstruction 2020-04-22 21:07:09 +01:00
MerryMage
09d3c77d74 IR: Add masked shift IR instructions 
Also use these in the A64 frontend to avoid the need to mask the shift amount.
 2020-04-22 21:06:17 +01:00
Lioncash
af3614553b A64/impl: Move AccType and MemOp enum into general IR emitter header 
These will be used by both frontends in the future, so this performs the
migratory changes separate from the changes that will make use of them.
 2020-04-22 21:04:23 +01:00
Lioncash
c6f99235e1 frontend/ir/ir_emitter: Remove unnecessary logical shift overloads 
These aren't necessary anymore, now that the U32U64 overload already
exists.
 2020-04-22 21:02:46 +01:00
Merry
09ee64ea98 Merge pull request #482 from lioncash/fixedfp 
A64: Handle half-precision variants of FP->Fixed instructions
 2020-04-22 21:02:45 +01:00
Lioncash
604f39f00a frontend/ir_emitter: Add half-precision->fixed-point opcodes 2020-04-22 21:01:45 +01:00
Merry
45864133f5 Merge pull request #478 from lioncash/stepfused 
A64: Handle half-precision variants of FRECPE and FRECPS
 2020-04-22 21:01:44 +01:00
Lioncash
824c551ba2 frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused 2020-04-22 21:01:44 +01:00
Lioncash
5dba99b4f4 frontend/ir_emitter: Add half-precision opcode variant for FPRSqrtEstimate 2020-04-22 21:01:44 +01:00
Lioncash
2184d24e8f frontend/ir_emitter: Add half-precision opcode for FPRecipEstimate 2020-04-22 21:01:44 +01:00
Lioncash
6da0411111 frontend/ir_emitter: Add half-precision opcode for FPRecipStepFused 2020-04-22 21:01:44 +01:00
Lioncash
ad0c698f89 frontend/ir_emitter: Add half-precision variant of FPRoundInt 2020-04-22 21:01:44 +01:00
Merry
cb9a1b18b6 Merge pull request #475 from lioncash/muladd 
A64: Enable half-precision variants of floating-point multiply-add instructions
 2020-04-22 21:01:44 +01:00
Lioncash
a4cadf1cd9 frontend/ir_emitter: Add opcodes for signed saturated left shifts with unsigned saturation 2020-04-22 21:01:44 +01:00
Lioncash
bd82513199 frontend/ir_emitter: Add half-precision opcode for FPMulAdd 2020-04-22 21:01:44 +01:00
Merry
01bb1cdd88 Merge pull request #458 from lioncash/float-op 
A64: Handle half-precision floating point in FABS, FNEG, and scalar FMOV
 2020-04-22 20:58:12 +01:00
Lioncash
8309ec7a9f frontend/ir_emitter: Add half-precision variant of FPAbs 2020-04-22 20:58:12 +01:00
Lioncash
e4c259d69f frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes 2020-04-22 20:58:12 +01:00
Lioncash
c97efcb978 frontend/ir_emitter: Add half-precision variant of FPNeg 2020-04-22 20:58:12 +01:00
Lioncash
bd892ec4ef frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point 2020-04-22 20:58:11 +01:00
Merry
fb039e232c Merge pull request #442 from lioncash/fcvtxn 
A64: Implement scalar and vector variants of FCVTXN
 2020-04-22 20:58:11 +01:00
Lioncash
5cf1478620 frontend/ir: Add opcodes for vector square roots 2020-04-22 20:58:10 +01:00
Lioncash
7c81a58ed3 frontend/ir/ir_emitter: Alter parameters of FPDoubleToSingle() and FPSingleToDouble() to pass along desired rounding mode 
This will be necessary to special-case the non-IEEE Von Neumann rounding
to odd rounding mode.
 2020-04-22 20:58:10 +01:00
Lioncash
9cf3c25811 frontend/ir/ir_emitter: Add opcodes for floating point reciprocal exponents 2020-04-22 20:58:10 +01:00
MerryMage
fa8925c4df IR: Implement FPVectorMulX 2020-04-22 20:57:37 +01:00
MerryMage
f0920c0ded Fix VShift terminology 
An arithmetic shift is by definition a signed shift, and a logical shift is by definition an unsigned shift.

- Rename VectorLogicalVShiftS* -> VectorArithmeticVShift*
- Rename VectorLogicalVShiftU* -> VectorLogicalVShift*
 2020-04-22 20:55:50 +01:00
Lioncash
d426dfe942 ir: Add opcodes for unsigned saturating left shifts 2020-04-22 20:55:06 +01:00
MerryMage
02150bc0b7 IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed 2020-04-22 20:55:06 +01:00
MerryMage
90193b0e3d IR: Add fbits argument to FixedToFP-related opcodes 2020-04-22 20:55:06 +01:00