Commit graph

1307 commits

Author SHA1 Message Date
Sebastian Valle
14eb70d7e4 VFP: Fixed the VCVT behavior when converting from unsigned 32-bit values. (#51)
Use a 64-bit register to hold the values so that we don't end up interpreting them as signed values.
2016-11-27 23:25:50 +00:00
Merry
0ff8c375af Implement UHSUB8 and UHSUB16 (#48) 2016-11-26 18:27:21 +00:00
Merry
cb17f9a3ed Implement SHADD8 and SHADD16 (#47) 2016-11-26 18:12:29 +00:00
Sebastian Valle
11ae8d1ffa Added disassembler support for the ARM parallel add/subtract (modulo arithmetic) instructions. (#50) 2016-11-26 17:58:09 +00:00
Sebastian Valle
ed71e31cea Added disassembler support for the ARM parallel and saturated instructions (#44) 2016-11-26 17:49:46 +00:00
Sebastian Valle
cda25c12b3 Added tests for the ARM parallel halving instructions. (#49) 2016-11-26 17:24:57 +00:00
MerryMage
c0c1bb1094 Implemented UHADD16 2016-11-26 11:28:20 +00:00
Mat M
4f7dc81492 mp: Fix static_assert condition (#46)
Not an issue currently, but this would have prevented type inspection on
the last function parameter.
2016-11-25 22:09:45 +00:00
Yuri Kunde Schlesner
700561a69a CMake: Add option to disable use of bundled fmtlib 2016-11-25 20:47:04 +00:00
Yuri Kunde Schlesner
9ec51f74bd libfmt: Update version to current master 2016-11-25 20:47:04 +00:00
Sebastian Valle
4d44474ad4 Implemented the ARM UHADD8 instruction. (#45)
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
2016-11-25 20:32:22 +00:00
Sebastian Valle
f32921d493 ARM: Implemented UXTB16. (#42)
It passes tests.
2016-11-24 08:21:12 +00:00
Sebastian Valle
32615d0eff Implemented the PKHTB and PKHBT instructions with tests. (#40) 2016-11-23 21:45:18 +00:00
MerryMage
780ff8e00e status_register_access: SEL: Use GetGEFlags 2016-11-23 19:47:35 +00:00
MerryMage
b6f7b8babd ir: Implement GetGEFlags, SetGEFlags 2016-11-23 19:44:27 +00:00
MerryMage
e7d02a5439 get_set_elimination_pass: Refactor CPSR related eliminations 2016-11-23 18:42:13 +00:00
MerryMage
4c817b9bd5 travis: No longer necessary to install latest cmake from homebrew on macOS 2016-11-23 18:24:06 +00:00
Sebastian Valle
d589c63107 Implemented the ARM SEL instruction, with tests. (#39)
The test for this instruction is very peculiar. As the instruction's behavior depends on the value of the CPSR, we generate a MSR instruction after each SEL instruction to change the CPSR.
2016-11-23 18:14:07 +00:00
MerryMage
6520c7537e travis: brew unlink is no longer necessary
xcode7.3 was updated with a newer version of cmake preinstalled
2016-09-21 17:53:28 +01:00
Mat M
65dcf45ca6 FPSCR: Mask away reserved bits (#34) 2016-09-21 17:51:13 +01:00
MerryMage
792f2bfd94 translate_arm: Remove unused method ArmTranslatorVisitor::LinkToNextInstruction 2016-09-21 14:07:53 +01:00
Mat M
f75acd6cfb decoder: Generify the matcher interface (#33)
Gets rid of a bit of duplication while remaining compatible
with the current interfaces in place.
2016-09-17 09:48:18 +01:00
Mat M
943487ecee disassembler: Provide includes to function declarations (#32) 2016-09-14 23:03:09 +01:00
Merry
b6c59d55a8 Update README.md 2016-09-13 14:54:22 +01:00
MerryMage
2c1818ece9 CMakeLists: Downgrade -msse4.1 to -msse3.
Virtually everyone supports SSE3 except for first-generation devices.
2016-09-11 16:21:35 +01:00
Mat M
72897b5def types: Provide ostream operator<< overloads where applicable (#30) 2016-09-07 14:21:17 +01:00
Mat M
b41de890fb memory_pool: Deduplicate slab allocation code (#28) 2016-09-07 13:20:42 +01:00
Merry
d646c3119d Merge pull request #29 from lioncash/list
intrusive_list: Minor changes
2016-09-07 12:10:05 +01:00
Mat M
6a2174ebfa Add missing explicit specifiers (#27) 2016-09-07 12:08:48 +01:00
Mat M
6e0f27a500 types: Add helpers for determining single and doubleword extension registers (#26) 2016-09-07 12:08:35 +01:00
Lioncash
c052f9f84c intrusive_list: Amend doxygen parameter documentation 2016-09-06 22:54:33 -04:00
Lioncash
1c4868ccce intrusive_list: Correct unused variable 2016-09-06 22:54:25 -04:00
Lioncash
8fb857f9da intrusive_list: Specify noexcept on swap implementations
Necessary to fully satisfy the Swappable concept.
2016-09-06 22:47:55 -04:00
Mat M
5bc9ce544f arm_types: Move into arm folder (#25) 2016-09-06 00:52:33 +01:00
Mat M
b40d19c3b7 location_descriptor: Provide operator<< string overload (#24) 2016-09-05 21:31:25 +01:00
MerryMage
5c8bf5a15d callbacks: CallSVC returns void 2016-09-05 19:15:45 +01:00
MerryMage
1f61a3d7bc jitstate: Rename fields s/guest_FPSCR/FPSCR/ 2016-09-05 14:42:21 +01:00
Mat M
6d53bb6d7e arm_types: Split out LocationDescriptor (#20)
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
2016-09-05 11:54:09 +01:00
Mat M
84336cf29d value: Change Value into a class (#19)
'struct' is a little bit of a misnomer, considering it has invariants
2016-09-05 11:53:56 +01:00
Mat M
858796a029 Eliminate variable shadowing warnings with MSVC (#17) 2016-09-04 11:30:57 +01:00
Mat M
7f9a0c3c38 Remove unnecessary explicit includes (#16) 2016-09-03 21:48:03 +01:00
Mat M
26db11cd71 reg_alloc: Use a strongly-typed enum for representing OpArg type (#15) 2016-09-03 18:30:03 +01:00
Mat M
05b189bc26 arm_types: Specialize std::hash for LocationDescriptor (#14)
Same thing, but with the benefit of working with anything that uses
std::hash by default.
2016-09-03 12:48:47 +01:00
Mat M
8c4df46580 FPSCR: Make value constructor explicit (#13)
Maintains consistency between the PSR helper.
2016-09-03 12:48:31 +01:00
Mat M
3e03524658 assert: Use attribute specifier syntax with non MSVC compilers (#12) 2016-09-03 12:48:07 +01:00
MerryMage
cc3e7e71aa bit_util: std::bitset-based BitCount implementation
Suggestion by @lioncash.
2016-09-02 22:00:48 +01:00
Mat M
5aa4f753b6 load_store: Add checks for unpredictability to other singular store instructions (#11) 2016-09-02 21:10:28 +01:00
MerryMage
e8764c129f bit_util: Implement BitCount portably 2016-09-02 19:05:49 +01:00
Mat M
6ec651498d arm: Add PSR helper type (#3) 2016-09-02 17:34:33 +01:00
Mat M
00d0f4d5ff load_store: Add correctness checks for STRD variants (#7)
STRD doesn't allow the use of the PC in either Rt or Rt2
2016-09-02 17:32:02 +01:00