Commit graph

44 commits

Author SHA1 Message Date
Lioncash
fe95575b95 general: Replace unreachable-imitating assertions with UNREACHABLE()
We can just use the self-documenting assertion for indicating
unreachable paths, instead of manually passing false and providing a
message.
2020-04-22 21:01:43 +01:00
Lioncash
7c81a58ed3 frontend/ir/ir_emitter: Alter parameters of FPDoubleToSingle() and FPSingleToDouble() to pass along desired rounding mode
This will be necessary to special-case the non-IEEE Von Neumann rounding
to odd rounding mode.
2020-04-22 20:58:10 +01:00
Lioncash
05a6ab691d translate_arm/coprocessor: Minor tidying up 2020-04-22 20:58:10 +01:00
Lioncash
1e32a09c03 translate_arm/vfp2: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
e209b31073 translate_arm/synchronization: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
9514e3602e translate_arm/status_register_access: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c6aa1a708a translate_arm/saturated: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
a72813599a translate_arm/reversal: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
7be56e6b67 translate_arm/parallel: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
3c00a616d6 translate_arm/packing: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c711188f46 translate_arm/multiply: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c8dad40d81 translate_arm/misc: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
a7bf5ff77d translate_arm/load_store: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
f4b19a7393 translate_arm/extension: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
c2de6ecfd0 translate_arm/exception_generating: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
d8a8d3b073 translate_arm/data_processing: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
df5c51ff47 translate_arm/branch: Invert conditionals where applicable
Allows unindenting code a bit.
2020-04-22 20:58:09 +01:00
V.Kalyuzhny
764a93bf5a Switch boost::optional to std::optional 2020-04-22 20:57:37 +01:00
MerryMage
90193b0e3d IR: Add fbits argument to FixedToFP-related opcodes 2020-04-22 20:55:06 +01:00
MerryMage
f96c43d422 A32: Implement FastDispatchHint 2020-04-22 20:53:46 +01:00
MerryMage
3415828fb4 IR: Simplify FP{Single,Double}ToFixed{U,S}{32,64} 2020-04-22 20:53:46 +01:00
MerryMage
f0184c4b8d a32/exception_generating: BPKT: Define unpredictable behaviour
Define unpredictable behaviour to be BKPT executes conditionally
2020-04-22 20:53:46 +01:00
MerryMage
a12854857b A32: Add define_unpredictable_behaviour option 2020-04-22 20:53:46 +01:00
MerryMage
71e137715d status_register_access: Add support for bits 0 and 1 of mask to MSR 2020-04-22 20:46:23 +01:00
MerryMage
ac51c2547d A32/translate/load_store: Correct detection of writeback 2020-04-22 20:46:23 +01:00
MerryMage
d345220251 A32/translate: Add TranslateSingleInstruction 2020-04-22 20:46:23 +01:00
Lioncash
9db6d1e98b translate_arm: Remove unnecessary rotr() function
We already have RotateRight() in our common code, so we can remove this
function and replace it with it. We can also implement ArmExpandImm_C()
in terms of ArmExpandImm().
2020-04-22 20:46:20 +01:00
MerryMage
caaf36dfd6 IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}
This implementation just falls-back to the software floating point implementation.
2020-04-22 20:46:19 +01:00
Lioncash
6bcfdba1ad general: Remove unused lambda captures
Resolves warnings that occur in Xcode 9.3
2020-04-22 20:46:16 +01:00
MerryMage
575590d18d ir_emitter: Remove overloads
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
2020-04-22 20:46:15 +01:00
MerryMage
aac5af50e2 IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them 2020-04-22 20:46:13 +01:00
MerryMage
429dc24587 IR: Merge U32 and U64 variants of FP instructions 2020-04-22 20:46:13 +01:00
MerryMage
cc0eb18a0b A32: data_processing: Remove !S assertions 2020-04-22 20:46:12 +01:00
MerryMage
865a30eb0d A32: Implement BKPT 2020-04-22 20:46:12 +01:00
MerryMage
f023bbb893 A32: Add ExceptionRaised IR instruction and use it 2020-04-22 20:46:12 +01:00
MerryMage
98ec9c5f90 A32: Change UserCallbacks to be similar to A64's interface 2020-04-22 20:46:12 +01:00
Lioncash
67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
2020-04-22 20:44:38 +01:00
MerryMage
5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
2020-04-22 20:42:46 +01:00
MerryMage
61125d6dd1 A64/translate: Add TranslateSingleInstruction function 2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00
MerryMage
d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00
MerryMage
f61da0b5a9 IR: Compile-time type-checking of IR 2020-04-22 20:39:27 +01:00
MerryMage
b1f0cf9278 A32: Split off A32 specific IREmitter 2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622 Label A32 specific code appropriately 2020-04-22 20:33:30 +01:00