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  • ab5efe8632 A32: Implement ASIMD VQDMULH (scalar) Lioncash 2020-06-23 01:35:37 -0400
  • 2008fda88b emit_x64_floating_point: Correct error in s16 rounding in EmitFPToFixed MerryMage 2020-06-22 22:54:38 +0100
  • 3ea49fc6d6 A32: Implement VFPv3 VCT (between floating-point and fixed-point) MerryMage 2020-06-22 21:03:20 +0100
  • 48b2ffdde9 A32: Implement ASIMD VQMOVUN, VQMOVN MerryMage 2020-06-22 20:02:52 +0100
  • 52b8039367 A32: Implement VFPv5 VRINT{R,Z} MerryMage 2020-06-22 19:35:32 +0100
  • 47bc99ad9f asimd_load_store_structures: Fix 2-byte aligned vld1.16 MerryMage 2020-06-22 18:46:06 +0100
  • dd8d5497da A32: Implement ASIMD VQRDMULH Lioncash 2020-06-21 20:47:28 -0400
  • 0b7a111b54 A32: Implement ASIMD VQDMULH Lioncash 2020-06-21 20:42:38 -0400
  • 39488e4aad A32: Implement ASIMD VRSHRN Lioncash 2020-06-21 17:41:15 -0400
  • 86b0e5c1c5 A32: Implement ASIMD VQSHRN Lioncash 2020-06-21 17:39:06 -0400
  • 85222e3e65 A32: Implement ASIMD VQSHRUN Lioncash 2020-06-21 17:32:38 -0400
  • 562a98bcf9 A32: Implement ASIMD VCVT (between floating-point and fixed-point) MerryMage 2020-06-21 20:22:39 +0100
  • 6f56043a73 A32: Implement ASIMD VFMA, VFMS MerryMage 2020-06-21 20:08:42 +0100
  • aa0358d324 A32: Implement ASIMD VMLAL/VMLSL (integer) Lioncash 2020-06-21 14:31:20 -0400
  • eab26b404a A32: Implement ASIMD VABAL Lioncash 2020-06-21 14:22:57 -0400
  • 98581839ca A32: Implement ASIMD VABDL Lioncash 2020-06-21 14:18:57 -0400
  • db85e7ced5 asimd: Add missing three registers of different lengths instructions MerryMage 2020-06-21 19:54:32 +0100
  • 95919594d1 A32: Implement ASIMD VQSHL/VQSHLU (immediate) Lioncash 2020-06-21 13:49:04 -0400
  • 3557576ece A32: Implement ASIMD AESD, AESE, AESIMC, AESMC MerryMage 2020-06-21 18:34:44 +0100
  • 2fa1c1d13c A32: Allow cleaning up exclusive state from the interface. Fernando Sahmkow 2020-06-21 13:15:13 -0400
  • df58a429ee A32: Implement ASIMD VQRSHRN MerryMage 2020-06-21 17:40:03 +0100
  • 589d717af5 A32: Implement ASIMD VQRSHRUN MerryMage 2020-06-21 17:19:01 +0100
  • e009d99924 A32: Implement ASIMD VSHRN MerryMage 2020-06-21 17:09:56 +0100
  • 473949d486 asimd_load_store_structures: Suppress MSVC shift warning MerryMage 2020-06-21 16:29:51 +0100
  • 8f0f1cfd66 A32: Implement ASIMD VST{1,2,3,4} (single n-element structure from one lane) MerryMage 2020-06-21 16:27:33 +0100
  • fa145ae401 a32_unicorn: Print code on unicorn error MerryMage 2020-06-21 16:23:01 +0100
  • 5a597f415c A32: Implement A32 VLD{1,2,3,4} (single n-element structure to one lane) MerryMage 2020-06-21 16:08:28 +0100
  • f221912409 bit_util: Bits without template arguments MerryMage 2020-06-21 16:07:59 +0100
  • 3202e4c539 A32: Implement ASIMD VLD{1,2,3,4} (single n-element structure to all lanes) MerryMage 2020-06-21 15:25:26 +0100
  • d7197745ac emit_x64_vector_floating_point: fpcr_controlled is unused when fsize == 16 in EmitFPVectorToFixed MerryMage 2020-06-21 14:34:42 +0100
  • b32fc5ab0f a64_emit_x64: EmitVAddrLookup: Use bzhi instruction when silently_mirror_page_table is active and BMI2 is available MerryMage 2020-06-21 14:32:48 +0100
  • 809dfe9c54 A32: Implement ASIMD VCVT (between floating-point and integer) MerryMage 2020-06-21 14:03:39 +0100
  • 43a4b2a0b8 ir_emitter: Remove dummy fpcr_controlled arguments from scalar FP instructions MerryMage 2020-06-21 13:57:34 +0100
  • c836b389c8 emit_x64_vector_floating_point: Add fpcr_controlled argument to all IR instructions MerryMage 2020-06-21 13:55:21 +0100
  • 33a81dae68 asimd: VEXT was being shadowed MerryMage 2020-06-21 13:12:19 +0100
  • bf093395d8 A32: Implement ASIMD VMOVN MerryMage 2020-06-21 12:19:02 +0100
  • c7785cd982 A32: Implement ASIMD VUZP and VZIP MerryMage 2020-06-21 12:04:03 +0100
  • 603cd09c8f A32: Implement ASIMD VTRN MerryMage 2020-06-21 11:44:27 +0100
  • a8b481ab63 simd_permute: Implement TRN{1,2} in terms of VectorTranspose MerryMage 2020-06-21 11:37:02 +0100
  • 7d1e103ff5 IR: Implement VectorTranspose MerryMage 2020-06-21 11:10:14 +0100
  • 9cc11681dc A32: Implement ASIMD VMLAL, VMLSL, VMULL (scalar) MerryMage 2020-06-21 10:30:10 +0100
  • 69a1d58a2b A32: Implement ASIMD VMULL MerryMage 2020-06-21 10:00:24 +0100
  • 8c23f02330 A32: Implement ASIMD VABD Lioncash 2020-06-20 21:37:43 -0400
  • fc1633a2ea A32: Implement ASIMD VABA Lioncash 2020-06-20 21:29:59 -0400
  • bdb92f7055 asimd: Split out VABA/VABD decoders Lioncash 2020-06-20 20:52:57 -0400
  • 230fa02648 A32: Implement ASIMD VMLA/VMLS (scalar) Lioncash 2020-06-20 20:30:03 -0400
  • 70d071e6ab fuzz_arm: Test large random blocks MerryMage 2020-06-21 00:36:33 +0100
  • 239ee289cf A32: Implement VDUP (scalar) MerryMage 2020-06-21 00:22:33 +0100
  • a8efe3f0f5 A32: Implement ASIMD VACGE/VACGT Lioncash 2020-06-20 17:49:49 -0400
  • e319257ec0 A32: Implement VCEQ/VCGE/VCGT (floating point) Lioncash 2020-06-20 17:27:55 -0400
  • faefb264a6 A32: Implement ASIMD VCEQ (integer) Lioncash 2020-06-20 17:02:36 -0400
  • 7276993352 A32: Implement ASIMD VCGE (integer) Lioncash 2020-06-20 16:49:12 -0400
  • 7292320445 A32: Implement ASIMD VCGT (integer) Lioncash 2020-06-20 16:43:30 -0400
  • fda4e11887 A32: Implement ASIMD VMOV (general-purpose register to scalar) MerryMage 2020-06-20 23:40:48 +0100
  • 7ec22b4e1d A32: Implement ASIMD VMOV (scalar to general-purpose register) MerryMage 2020-06-20 23:24:35 +0100
  • 8bbc9fdbb6 A32: Implement ASIMD VTBX MerryMage 2020-06-20 22:34:55 +0100
  • 06f7229c57 A32: Implement ASIMD VPADAL (integer) Lioncash 2020-06-20 15:48:20 -0400
  • 266c6a2000 A32: Implement ASIMD VPADDL (integer) Lioncash 2020-06-20 15:39:41 -0400
  • 4bb286ac23 A32: Implement ASIMD VPADD (integer) Lioncash 2020-06-20 14:59:57 -0400
  • 1ffeeeb6a2 A32: Implement ASIMD VMAX/VMIN (integer) Lioncash 2020-06-20 14:52:10 -0400
  • 945b757b6c A32: Implement ASIMD VMLA/VMLS (integer) Lioncash 2020-06-20 14:41:56 -0400
  • 715db8381f A32: Implement ASIMD VMUL (scalar) MerryMage 2020-06-20 20:08:11 +0100
  • b0beecdd41 A32: Implement ASIMD VTBL MerryMage 2020-06-20 19:25:14 +0100
  • 28f27bc19d A32: Implement ASIMD VEXT MerryMage 2020-06-20 19:01:00 +0100
  • e8c460c167 A32: Implement ASIMD VDUP (ARM core register) MerryMage 2020-06-20 15:58:29 +0100
  • 15ee562dd0 decoder/asimd: Add misc data-processing instructions MerryMage 2020-06-20 15:39:00 +0100
  • 214c1d6002 fuzz_arm: Test testable parts of ASIMD VRECPE and VRSQRTE MerryMage 2020-06-20 15:17:08 +0100
  • 92cb4a5a34 A32: Implement ASIMD VRSQRTE MerryMage 2020-06-20 15:13:18 +0100
  • 8912496206 fuzz_arm: Unicorn has incorrect VRSQRTS implementation MerryMage 2020-06-20 15:07:50 +0100
  • 6f59c2cd8e A32: Implement ASIMD VRECPE MerryMage 2020-06-20 15:07:06 +0100
  • d3dc50d718 A32: Implement ASIMD VRSQRTS MerryMage 2020-06-20 14:45:29 +0100
  • 8f506c80c3 A32: Implement ASIMD VRECPS MerryMage 2020-06-20 14:39:05 +0100
  • 9eef4f7471 A32: Implement ASIMD VMLA, VMLS (floating-point) MerryMage 2020-06-20 14:29:37 +0100
  • 60f6e729ac A32: Implement ASIMD VABD (floating-point) MerryMage 2020-06-20 14:02:26 +0100
  • f58e247ef3 A32: Implement ASIMD VPADD (floating-point) MerryMage 2020-06-20 13:55:28 +0100
  • e006f0a205 A32: Implement ASIMD VSUB (floating-point) MerryMage 2020-06-20 13:39:03 +0100
  • 4c939b9d0a A32: Implement ASIMD VADD (floating-point) MerryMage 2020-06-20 13:36:14 +0100
  • 5ec8e48593 A32: Implement ASIMD VMUL (floating-point) MerryMage 2020-06-20 13:33:45 +0100
  • bb4f3aa407 A32: Implement ASIMD VMAX, VMIN (floating-point) MerryMage 2020-06-20 01:18:17 +0100
  • 8d067d5d60 A32: Implement ASIMD VMUL (integer and polynomial) Lioncash 2020-06-19 17:00:53 -0400
  • ed6ca58058 A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero Lioncash 2020-06-20 00:05:58 +0100
  • 656419286c ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual} MerryMage 2020-06-20 00:01:10 +0100
  • 1b3a70a83c backend/x64: Implement separate MSXCSR for ASIMDStandardValue MerryMage 2020-06-20 00:00:36 +0100
  • d3664b03fe ir_emitter: Default fpcr_controlled arguments to true MerryMage 2020-06-19 22:46:19 +0100
  • 794440cf8d A32: Implement ASIMD VRSHL Lioncash 2020-06-19 13:46:19 -0400
  • 682621ef1a A32: Implement ASIMD VQSHL (register) Lioncash 2020-06-19 13:39:43 -0400
  • e46fb98cc5 A32: Implement ASIMD VSHL (register) Lioncash 2020-06-19 13:35:00 -0400
  • ad96b2b18d VFPv5: Implement VCVT{A,N,P,M} MerryMage 2020-06-19 20:31:16 +0100
  • 6a965b80d6 VFPv5: Implement VRINT{A,N,P,M} MerryMage 2020-06-19 20:21:21 +0100
  • 3e252cdbfc VFPv5: Implement VSEL MerryMage 2020-06-19 19:40:39 +0100
  • 669d05caca VFPv5: Implement VMINNM MerryMage 2020-06-19 19:33:01 +0100
  • 6e7ea151a3 VFPv5: Implement VMAXNM MerryMage 2020-06-19 19:29:23 +0100
  • 4df3b2f97f vfp: Add decoders for VFPv5 MerryMage 2020-06-19 19:24:05 +0100
  • 55c021fe82 emit_x64_aes: AESNI implementations of all opcodes MerryMage 2020-06-19 12:11:35 +0100
  • 551e207661 A32: Implement ASIMD VSUB (integer) Lioncash 2020-06-18 22:18:54 -0400
  • 4d6f68525d A32: Implement ASIMD VADD (integer) Lioncash 2020-06-18 22:16:44 -0400
  • fbdae61c13 A32: Implement ASIMD VMVN (register) Lioncash 2020-06-18 21:58:17 -0400
  • b759773b3b a32_emit_x64: EmitVAddrLookup: Use 64-bit registers where required MerryMage 2020-06-19 00:44:37 +0100
  • 687c604197
         Merge pull request #532 from lioncash/shift merry 2020-06-19 00:22:18 +0100
  • 7dd9901de2 a32_emit_x64: Incorrect type in ExclusiveWriteMemory MerryMage 2020-06-19 00:19:46 +0100