2018-01-06 21:15:25 +00:00
|
|
|
/* This file is part of the dynarmic project.
|
|
|
|
* Copyright (c) 2016 MerryMage
|
|
|
|
* This software may be used and distributed according to the terms of the GNU
|
|
|
|
* General Public License version 2 or any later version.
|
|
|
|
*/
|
|
|
|
|
2018-02-12 19:49:56 +00:00
|
|
|
#include <initializer_list>
|
|
|
|
|
2018-06-05 12:27:37 +01:00
|
|
|
#include <dynarmic/A64/exclusive_monitor.h>
|
2018-07-27 12:42:10 +01:00
|
|
|
#include <fmt/format.h>
|
2018-01-27 23:42:30 +00:00
|
|
|
#include <fmt/ostream.h>
|
|
|
|
|
2018-08-14 19:13:47 +01:00
|
|
|
#include "backend/x64/a64_emit_x64.h"
|
|
|
|
#include "backend/x64/a64_jitstate.h"
|
|
|
|
#include "backend/x64/abi.h"
|
|
|
|
#include "backend/x64/block_of_code.h"
|
|
|
|
#include "backend/x64/devirtualize.h"
|
|
|
|
#include "backend/x64/emit_x64.h"
|
2018-07-27 12:42:10 +01:00
|
|
|
#include "backend/x64/perf_map.h"
|
2018-01-06 21:15:25 +00:00
|
|
|
#include "common/assert.h"
|
|
|
|
#include "common/bit_util.h"
|
|
|
|
#include "common/common_types.h"
|
2018-08-22 13:16:26 +01:00
|
|
|
#include "common/scope_exit.h"
|
2018-01-06 21:15:25 +00:00
|
|
|
#include "common/variant_util.h"
|
|
|
|
#include "frontend/A64/location_descriptor.h"
|
|
|
|
#include "frontend/A64/types.h"
|
|
|
|
#include "frontend/ir/basic_block.h"
|
|
|
|
#include "frontend/ir/microinstruction.h"
|
|
|
|
#include "frontend/ir/opcodes.h"
|
|
|
|
|
|
|
|
// TODO: Have ARM flags in host flags and not have them use up GPR registers unless necessary.
|
|
|
|
// TODO: Actually implement that proper instruction selector you've always wanted to sweetheart.
|
|
|
|
|
2018-01-26 13:51:48 +00:00
|
|
|
namespace Dynarmic::BackendX64 {
|
2018-01-06 21:15:25 +00:00
|
|
|
|
|
|
|
using namespace Xbyak::util;
|
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
A64EmitContext::A64EmitContext(const A64::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block)
|
|
|
|
: EmitContext(reg_alloc, block), conf(conf) {}
|
2018-01-06 21:15:25 +00:00
|
|
|
|
|
|
|
A64::LocationDescriptor A64EmitContext::Location() const {
|
|
|
|
return A64::LocationDescriptor{block.Location()};
|
|
|
|
}
|
|
|
|
|
2019-03-24 10:59:44 +00:00
|
|
|
FP::FPCR A64EmitContext::FPCR() const {
|
|
|
|
return Location().FPCR();
|
2018-02-18 13:04:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool A64EmitContext::AccurateNaN() const {
|
|
|
|
return conf.floating_point_nan_accuracy == A64::UserConfig::NaNAccuracy::Accurate;
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-08-18 01:20:42 +01:00
|
|
|
A64EmitX64::A64EmitX64(BlockOfCode& code, A64::UserConfig conf, A64::Jit* jit_interface)
|
2018-09-07 21:51:42 +01:00
|
|
|
: EmitX64(code), conf(conf), jit_interface{jit_interface} {
|
2018-02-12 18:18:47 +00:00
|
|
|
GenMemory128Accessors();
|
2018-02-12 19:49:56 +00:00
|
|
|
GenFastmemFallbacks();
|
2018-09-07 21:51:42 +01:00
|
|
|
GenTerminalHandlers();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.PreludeComplete();
|
2018-09-07 21:51:42 +01:00
|
|
|
ClearFastDispatchTable();
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-01-24 02:11:07 +00:00
|
|
|
A64EmitX64::~A64EmitX64() = default;
|
2018-01-06 21:15:25 +00:00
|
|
|
|
|
|
|
A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) {
|
2018-08-22 13:16:26 +01:00
|
|
|
code.EnableWriting();
|
|
|
|
SCOPE_EXIT { code.DisableWriting(); };
|
|
|
|
|
2018-02-03 14:28:57 +00:00
|
|
|
code.align();
|
|
|
|
const u8* const entrypoint = code.getCurr();
|
2018-01-06 21:15:25 +00:00
|
|
|
|
|
|
|
// Start emitting.
|
|
|
|
EmitCondPrelude(block);
|
|
|
|
|
|
|
|
RegAlloc reg_alloc{code, A64JitState::SpillCount, SpillToOpArg<A64JitState>};
|
2018-02-18 13:00:41 +00:00
|
|
|
A64EmitContext ctx{conf, reg_alloc, block};
|
2018-01-06 21:15:25 +00:00
|
|
|
|
|
|
|
for (auto iter = block.begin(); iter != block.end(); ++iter) {
|
|
|
|
IR::Inst* inst = &*iter;
|
|
|
|
|
|
|
|
// Call the relevant Emit* member function.
|
|
|
|
switch (inst->GetOpcode()) {
|
|
|
|
|
|
|
|
#define OPCODE(name, type, ...) \
|
|
|
|
case IR::Opcode::name: \
|
|
|
|
A64EmitX64::Emit##name(ctx, inst); \
|
|
|
|
break;
|
|
|
|
#define A32OPC(...)
|
|
|
|
#define A64OPC(name, type, ...) \
|
|
|
|
case IR::Opcode::A64##name: \
|
|
|
|
A64EmitX64::EmitA64##name(ctx, inst); \
|
|
|
|
break;
|
|
|
|
#include "frontend/ir/opcodes.inc"
|
|
|
|
#undef OPCODE
|
|
|
|
#undef A32OPC
|
|
|
|
#undef A64OPC
|
|
|
|
|
|
|
|
default:
|
2018-01-27 23:42:30 +00:00
|
|
|
ASSERT_MSG(false, "Invalid opcode: {}", inst->GetOpcode());
|
2018-01-06 21:15:25 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-01-10 02:05:08 +00:00
|
|
|
ctx.reg_alloc.EndOfAllocScope();
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
reg_alloc.AssertNoMoreUses();
|
|
|
|
|
|
|
|
EmitAddCycles(block.CycleCount());
|
|
|
|
EmitX64::EmitTerminal(block.GetTerminal(), block.Location());
|
2018-02-03 14:28:57 +00:00
|
|
|
code.int3();
|
2018-01-06 21:15:25 +00:00
|
|
|
|
2018-02-03 14:28:57 +00:00
|
|
|
const size_t size = static_cast<size_t>(code.getCurr() - entrypoint);
|
2018-07-27 12:42:10 +01:00
|
|
|
|
|
|
|
const A64::LocationDescriptor descriptor{block.Location()};
|
2018-01-06 21:15:25 +00:00
|
|
|
const A64::LocationDescriptor end_location{block.EndLocation()};
|
2018-07-27 12:42:10 +01:00
|
|
|
|
2018-01-06 21:15:25 +00:00
|
|
|
const auto range = boost::icl::discrete_interval<u64>::closed(descriptor.PC(), end_location.PC() - 1);
|
2018-01-23 19:16:39 +00:00
|
|
|
block_ranges.AddRange(range, descriptor);
|
2018-01-06 21:15:25 +00:00
|
|
|
|
2018-07-27 12:42:10 +01:00
|
|
|
return RegisterBlock(descriptor, entrypoint, size);
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-01-23 19:16:39 +00:00
|
|
|
void A64EmitX64::ClearCache() {
|
|
|
|
EmitX64::ClearCache();
|
|
|
|
block_ranges.ClearCache();
|
2018-09-07 21:51:42 +01:00
|
|
|
ClearFastDispatchTable();
|
2018-01-23 19:16:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::InvalidateCacheRanges(const boost::icl::interval_set<u64>& ranges) {
|
|
|
|
InvalidateBasicBlocks(block_ranges.InvalidateRanges(ranges));
|
2018-09-07 21:51:42 +01:00
|
|
|
ClearFastDispatchTable();
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::ClearFastDispatchTable() {
|
2018-09-08 10:47:00 +01:00
|
|
|
if (conf.enable_fast_dispatch) {
|
|
|
|
fast_dispatch_table.fill({0xFFFFFFFFFFFFFFFFull, nullptr});
|
|
|
|
}
|
2018-01-23 19:16:39 +00:00
|
|
|
}
|
|
|
|
|
2018-02-12 18:18:47 +00:00
|
|
|
void A64EmitX64::GenMemory128Accessors() {
|
|
|
|
code.align();
|
|
|
|
memory_read_128 = code.getCurr<void(*)()>();
|
|
|
|
#ifdef _WIN32
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryRead128>(conf.callbacks).EmitCallWithReturnPointer(code,
|
|
|
|
[&](Xbyak::Reg64 return_value_ptr, RegList args) {
|
|
|
|
code.mov(code.ABI_PARAM3, code.ABI_PARAM2);
|
|
|
|
code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE);
|
|
|
|
code.lea(return_value_ptr, ptr[rsp + ABI_SHADOW_SPACE]);
|
|
|
|
});
|
2018-07-31 20:53:33 +01:00
|
|
|
code.movups(xmm1, xword[code.ABI_RETURN]);
|
2018-02-12 18:18:47 +00:00
|
|
|
code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE);
|
|
|
|
#else
|
|
|
|
code.sub(rsp, 8);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryRead128>(conf.callbacks).EmitCall(code);
|
2018-02-12 18:18:47 +00:00
|
|
|
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
2018-07-31 20:53:33 +01:00
|
|
|
code.movq(xmm1, code.ABI_RETURN);
|
|
|
|
code.pinsrq(xmm1, code.ABI_RETURN2, 1);
|
2018-02-12 18:18:47 +00:00
|
|
|
} else {
|
2018-07-31 20:53:33 +01:00
|
|
|
code.movq(xmm1, code.ABI_RETURN);
|
|
|
|
code.movq(xmm2, code.ABI_RETURN2);
|
|
|
|
code.punpcklqdq(xmm1, xmm2);
|
2018-02-12 18:18:47 +00:00
|
|
|
}
|
|
|
|
code.add(rsp, 8);
|
|
|
|
#endif
|
|
|
|
code.ret();
|
2018-07-27 12:42:10 +01:00
|
|
|
PerfMapRegister(memory_read_128, code.getCurr(), "a64_memory_read_128");
|
2018-02-12 18:18:47 +00:00
|
|
|
|
|
|
|
code.align();
|
|
|
|
memory_write_128 = code.getCurr<void(*)()>();
|
|
|
|
#ifdef _WIN32
|
|
|
|
code.sub(rsp, 8 + 16 + ABI_SHADOW_SPACE);
|
|
|
|
code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]);
|
2018-07-31 20:53:33 +01:00
|
|
|
code.movaps(xword[code.ABI_PARAM3], xmm1);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryWrite128>(conf.callbacks).EmitCall(code);
|
2018-02-12 18:18:47 +00:00
|
|
|
code.add(rsp, 8 + 16 + ABI_SHADOW_SPACE);
|
|
|
|
#else
|
|
|
|
code.sub(rsp, 8);
|
|
|
|
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE41)) {
|
2018-07-31 20:53:33 +01:00
|
|
|
code.movq(code.ABI_PARAM3, xmm1);
|
|
|
|
code.pextrq(code.ABI_PARAM4, xmm1, 1);
|
2018-02-12 18:18:47 +00:00
|
|
|
} else {
|
2018-07-31 20:53:33 +01:00
|
|
|
code.movq(code.ABI_PARAM3, xmm1);
|
|
|
|
code.punpckhqdq(xmm1, xmm1);
|
|
|
|
code.movq(code.ABI_PARAM4, xmm1);
|
2018-02-12 18:18:47 +00:00
|
|
|
}
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryWrite128>(conf.callbacks).EmitCall(code);
|
2018-02-12 18:18:47 +00:00
|
|
|
code.add(rsp, 8);
|
|
|
|
#endif
|
|
|
|
code.ret();
|
2018-07-27 12:42:10 +01:00
|
|
|
PerfMapRegister(memory_read_128, code.getCurr(), "a64_memory_write_128");
|
2018-02-12 18:18:47 +00:00
|
|
|
}
|
|
|
|
|
2018-02-12 19:49:56 +00:00
|
|
|
void A64EmitX64::GenFastmemFallbacks() {
|
|
|
|
const std::initializer_list<int> idxes{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
|
2018-11-24 01:11:08 +00:00
|
|
|
const std::array<std::pair<size_t, ArgCallback>, 4> read_callbacks{{
|
2018-08-03 09:09:29 +01:00
|
|
|
{8, Devirtualize<&A64::UserCallbacks::MemoryRead8>(conf.callbacks)},
|
|
|
|
{16, Devirtualize<&A64::UserCallbacks::MemoryRead16>(conf.callbacks)},
|
|
|
|
{32, Devirtualize<&A64::UserCallbacks::MemoryRead32>(conf.callbacks)},
|
|
|
|
{64, Devirtualize<&A64::UserCallbacks::MemoryRead64>(conf.callbacks)},
|
2018-11-24 01:11:08 +00:00
|
|
|
}};
|
|
|
|
const std::array<std::pair<size_t, ArgCallback>, 4> write_callbacks{{
|
2018-08-03 09:09:29 +01:00
|
|
|
{8, Devirtualize<&A64::UserCallbacks::MemoryWrite8>(conf.callbacks)},
|
|
|
|
{16, Devirtualize<&A64::UserCallbacks::MemoryWrite16>(conf.callbacks)},
|
|
|
|
{32, Devirtualize<&A64::UserCallbacks::MemoryWrite32>(conf.callbacks)},
|
|
|
|
{64, Devirtualize<&A64::UserCallbacks::MemoryWrite64>(conf.callbacks)},
|
2018-11-24 01:11:08 +00:00
|
|
|
}};
|
2018-02-12 19:49:56 +00:00
|
|
|
|
|
|
|
for (int vaddr_idx : idxes) {
|
|
|
|
if (vaddr_idx == 4 || vaddr_idx == 15) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int value_idx : idxes) {
|
|
|
|
code.align();
|
|
|
|
read_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
|
|
|
|
ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(value_idx));
|
|
|
|
if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
|
|
|
|
code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
|
|
|
|
}
|
|
|
|
code.call(memory_read_128);
|
2018-07-31 20:53:33 +01:00
|
|
|
if (value_idx != 1) {
|
|
|
|
code.movaps(Xbyak::Xmm{value_idx}, xmm1);
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
|
|
|
ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocXmmIdx(value_idx));
|
|
|
|
code.ret();
|
2018-07-27 12:42:10 +01:00
|
|
|
PerfMapRegister(read_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)], code.getCurr(), "a64_read_fallback_128");
|
2018-02-12 19:49:56 +00:00
|
|
|
|
|
|
|
code.align();
|
|
|
|
write_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
|
|
|
|
ABI_PushCallerSaveRegistersAndAdjustStack(code);
|
|
|
|
if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
|
|
|
|
code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
|
|
|
|
}
|
2018-07-31 20:53:33 +01:00
|
|
|
if (value_idx != 1) {
|
|
|
|
code.movaps(xmm1, Xbyak::Xmm{value_idx});
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
|
|
|
code.call(memory_write_128);
|
|
|
|
ABI_PopCallerSaveRegistersAndAdjustStack(code);
|
|
|
|
code.ret();
|
2018-07-27 12:42:10 +01:00
|
|
|
PerfMapRegister(write_fallbacks[std::make_tuple(128, vaddr_idx, value_idx)], code.getCurr(), "a64_write_fallback_128");
|
2018-02-12 19:49:56 +00:00
|
|
|
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
if (value_idx == 4 || value_idx == 15) {
|
2018-02-12 19:49:56 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-11-24 01:12:55 +00:00
|
|
|
for (const auto& [bitsize, callback] : read_callbacks) {
|
2018-02-12 19:49:56 +00:00
|
|
|
code.align();
|
|
|
|
read_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
|
|
|
|
ABI_PushCallerSaveRegistersAndAdjustStackExcept(code, HostLocRegIdx(value_idx));
|
|
|
|
if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
|
|
|
|
code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
|
|
|
|
}
|
|
|
|
callback.EmitCall(code);
|
|
|
|
if (value_idx != code.ABI_RETURN.getIdx()) {
|
|
|
|
code.mov(Xbyak::Reg64{value_idx}, code.ABI_RETURN);
|
|
|
|
}
|
|
|
|
ABI_PopCallerSaveRegistersAndAdjustStackExcept(code, HostLocRegIdx(value_idx));
|
|
|
|
code.ret();
|
2018-07-27 12:42:10 +01:00
|
|
|
PerfMapRegister(read_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)], code.getCurr(), fmt::format("a64_read_fallback_{}", bitsize));
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
|
|
|
|
2018-11-24 01:12:55 +00:00
|
|
|
for (const auto& [bitsize, callback] : write_callbacks) {
|
2018-02-12 19:49:56 +00:00
|
|
|
code.align();
|
|
|
|
write_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)] = code.getCurr<void(*)()>();
|
|
|
|
ABI_PushCallerSaveRegistersAndAdjustStack(code);
|
|
|
|
if (vaddr_idx == code.ABI_PARAM3.getIdx() && value_idx == code.ABI_PARAM2.getIdx()) {
|
|
|
|
code.xchg(code.ABI_PARAM2, code.ABI_PARAM3);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
} else if (vaddr_idx == code.ABI_PARAM3.getIdx()) {
|
|
|
|
code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
|
|
|
|
if (value_idx != code.ABI_PARAM3.getIdx()) {
|
|
|
|
code.mov(code.ABI_PARAM3, Xbyak::Reg64{value_idx});
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
} else {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (value_idx != code.ABI_PARAM3.getIdx()) {
|
|
|
|
code.mov(code.ABI_PARAM3, Xbyak::Reg64{value_idx});
|
|
|
|
}
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
if (vaddr_idx != code.ABI_PARAM2.getIdx()) {
|
|
|
|
code.mov(code.ABI_PARAM2, Xbyak::Reg64{vaddr_idx});
|
|
|
|
}
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
|
|
|
callback.EmitCall(code);
|
|
|
|
ABI_PopCallerSaveRegistersAndAdjustStack(code);
|
|
|
|
code.ret();
|
2018-07-27 12:42:10 +01:00
|
|
|
PerfMapRegister(write_fallbacks[std::make_tuple(bitsize, vaddr_idx, value_idx)], code.getCurr(), fmt::format("a64_write_fallback_{}", bitsize));
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-07 21:51:42 +01:00
|
|
|
void A64EmitX64::GenTerminalHandlers() {
|
|
|
|
// PC ends up in rbp, location_descriptor ends up in rbx
|
|
|
|
const auto calculate_location_descriptor = [this] {
|
|
|
|
// This calculation has to match up with A64::LocationDescriptor::UniqueHash
|
2019-05-05 19:45:45 +01:00
|
|
|
// TODO: Optimization is available here based on known state of fpcr.
|
2018-09-07 21:51:42 +01:00
|
|
|
code.mov(rbp, qword[r15 + offsetof(A64JitState, pc)]);
|
|
|
|
code.mov(rcx, A64::LocationDescriptor::PC_MASK);
|
|
|
|
code.and_(rcx, rbp);
|
|
|
|
code.mov(ebx, dword[r15 + offsetof(A64JitState, fpcr)]);
|
|
|
|
code.and_(ebx, A64::LocationDescriptor::FPCR_MASK);
|
|
|
|
code.shl(ebx, 37);
|
|
|
|
code.or_(rbx, rcx);
|
|
|
|
};
|
|
|
|
|
|
|
|
Xbyak::Label fast_dispatch_cache_miss, rsb_cache_miss;
|
|
|
|
|
|
|
|
code.align();
|
|
|
|
terminal_handler_pop_rsb_hint = code.getCurr<const void*>();
|
|
|
|
calculate_location_descriptor();
|
|
|
|
code.mov(eax, dword[r15 + offsetof(A64JitState, rsb_ptr)]);
|
|
|
|
code.sub(eax, 1);
|
|
|
|
code.and_(eax, u32(A64JitState::RSBPtrMask));
|
|
|
|
code.mov(dword[r15 + offsetof(A64JitState, rsb_ptr)], eax);
|
|
|
|
code.cmp(rbx, qword[r15 + offsetof(A64JitState, rsb_location_descriptors) + rax * sizeof(u64)]);
|
|
|
|
if (conf.enable_fast_dispatch) {
|
|
|
|
code.jne(rsb_cache_miss);
|
|
|
|
} else {
|
|
|
|
code.jne(code.GetReturnFromRunCodeAddress());
|
|
|
|
}
|
|
|
|
code.mov(rax, qword[r15 + offsetof(A64JitState, rsb_codeptrs) + rax * sizeof(u64)]);
|
|
|
|
code.jmp(rax);
|
|
|
|
PerfMapRegister(terminal_handler_pop_rsb_hint, code.getCurr(), "a64_terminal_handler_pop_rsb_hint");
|
|
|
|
|
|
|
|
if (conf.enable_fast_dispatch) {
|
|
|
|
code.align();
|
|
|
|
terminal_handler_fast_dispatch_hint = code.getCurr<const void*>();
|
|
|
|
calculate_location_descriptor();
|
|
|
|
code.L(rsb_cache_miss);
|
|
|
|
code.mov(r12, reinterpret_cast<u64>(fast_dispatch_table.data()));
|
|
|
|
if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSE42)) {
|
|
|
|
code.crc32(rbp, r12d);
|
|
|
|
}
|
|
|
|
code.and_(ebp, fast_dispatch_table_mask);
|
|
|
|
code.lea(rbp, ptr[r12 + rbp]);
|
|
|
|
code.cmp(rbx, qword[rbp + offsetof(FastDispatchEntry, location_descriptor)]);
|
|
|
|
code.jne(fast_dispatch_cache_miss);
|
|
|
|
code.jmp(ptr[rbp + offsetof(FastDispatchEntry, code_ptr)]);
|
|
|
|
code.L(fast_dispatch_cache_miss);
|
|
|
|
code.mov(qword[rbp + offsetof(FastDispatchEntry, location_descriptor)], rbx);
|
|
|
|
code.LookupBlock();
|
|
|
|
code.mov(ptr[rbp + offsetof(FastDispatchEntry, code_ptr)], rax);
|
|
|
|
code.jmp(rax);
|
|
|
|
PerfMapRegister(terminal_handler_fast_dispatch_hint, code.getCurr(), "a64_terminal_handler_fast_dispatch_hint");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-07 16:33:02 +00:00
|
|
|
void A64EmitX64::EmitA64SetCheckBit(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg8 to_store = ctx.reg_alloc.UseGpr(args[0]).cvt8();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, check_bit)], to_store);
|
2018-01-07 16:33:02 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 11:31:20 +00:00
|
|
|
void A64EmitX64::EmitA64GetCFlag(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2019-05-05 19:49:54 +01:00
|
|
|
code.mov(result, dword[r15 + offsetof(A64JitState, cpsr_nzcv)]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.shr(result, 29);
|
|
|
|
code.and_(result, 1);
|
2018-01-07 11:31:20 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2019-03-06 18:54:09 +00:00
|
|
|
void A64EmitX64::EmitA64GetNZCVRaw(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
const Xbyak::Reg32 nzcv_raw = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
|
|
|
2019-05-05 19:49:54 +01:00
|
|
|
code.mov(nzcv_raw, dword[r15 + offsetof(A64JitState, cpsr_nzcv)]);
|
2019-03-06 18:54:09 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, nzcv_raw);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetNZCVRaw(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
const Xbyak::Reg32 nzcv_raw = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
|
|
|
|
|
|
|
|
code.and_(nzcv_raw, 0xF0000000);
|
2019-05-05 19:49:54 +01:00
|
|
|
code.mov(dword[r15 + offsetof(A64JitState, cpsr_nzcv)], nzcv_raw);
|
2019-03-06 18:54:09 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 11:31:20 +00:00
|
|
|
void A64EmitX64::EmitA64SetNZCV(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg32 to_store = ctx.reg_alloc.UseScratchGpr(args[0]).cvt32();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.and_(to_store, 0b11000001'00000001);
|
|
|
|
code.imul(to_store, to_store, 0b00010000'00100001);
|
|
|
|
code.shl(to_store, 16);
|
|
|
|
code.and_(to_store, 0xF0000000);
|
2019-05-05 19:49:54 +01:00
|
|
|
code.mov(dword[r15 + offsetof(A64JitState, cpsr_nzcv)], to_store);
|
2018-01-07 11:31:20 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
|
|
void A64EmitX64::EmitA64GetW(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
|
|
|
const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-01-07 00:11:57 +00:00
|
|
|
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(result, dword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)]);
|
2018-01-07 00:11:57 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64GetX(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
|
|
|
const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
2018-01-07 00:11:57 +00:00
|
|
|
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(result, qword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)]);
|
2018-01-07 00:11:57 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-01-26 18:35:19 +00:00
|
|
|
void A64EmitX64::EmitA64GetS(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
const auto addr = qword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-26 18:35:19 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movd(result, addr);
|
2018-01-26 18:35:19 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-01-21 17:45:43 +00:00
|
|
|
void A64EmitX64::EmitA64GetD(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
const auto addr = qword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-21 17:45:43 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(result, addr);
|
2018-01-21 17:45:43 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64GetQ(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
const auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-21 17:45:43 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movaps(result, addr);
|
2018-01-21 17:45:43 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-01-07 11:31:20 +00:00
|
|
|
void A64EmitX64::EmitA64GetSP(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(result, qword[r15 + offsetof(A64JitState, sp)]);
|
2018-01-07 11:31:20 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-20 17:38:29 +00:00
|
|
|
void A64EmitX64::EmitA64GetFPCR(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-02-20 20:29:15 +00:00
|
|
|
code.mov(result, dword[r15 + offsetof(A64JitState, fpcr)]);
|
2018-02-20 17:38:29 +00:00
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 GetFPSRImpl(A64JitState* jit_state) {
|
|
|
|
return jit_state->GetFpsr();
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64GetFPSR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
ctx.reg_alloc.HostCall(inst);
|
|
|
|
code.mov(code.ABI_PARAM1, code.r15);
|
|
|
|
code.stmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
|
|
|
|
code.CallFunction(GetFPSRImpl);
|
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
|
|
void A64EmitX64::EmitA64SetW(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
|
|
|
const auto addr = qword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)];
|
2018-01-15 21:47:28 +00:00
|
|
|
if (args[1].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[1].GetImmediateS32());
|
2018-01-07 00:11:57 +00:00
|
|
|
} else {
|
2018-01-09 21:21:15 +00:00
|
|
|
// TODO: zext tracking, xmm variant
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 to_store = ctx.reg_alloc.UseScratchGpr(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(to_store.cvt32(), to_store.cvt32());
|
|
|
|
code.mov(addr, to_store);
|
2018-01-07 00:11:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetX(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Reg reg = inst->GetArg(0).GetA64RegRef();
|
|
|
|
const auto addr = qword[r15 + offsetof(A64JitState, reg) + sizeof(u64) * static_cast<size_t>(reg)];
|
2018-01-13 17:59:50 +00:00
|
|
|
if (args[1].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[1].GetImmediateS32());
|
2018-01-07 00:11:57 +00:00
|
|
|
} else if (args[1].IsInXmm()) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(addr, to_store);
|
2018-01-07 00:11:57 +00:00
|
|
|
} else {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 to_store = ctx.reg_alloc.UseGpr(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, to_store);
|
2018-01-07 00:11:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-26 18:34:22 +00:00
|
|
|
void A64EmitX64::EmitA64SetS(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
const auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-26 18:34:22 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[1]);
|
|
|
|
const Xbyak::Xmm tmp = ctx.reg_alloc.ScratchXmm();
|
2018-01-26 18:34:22 +00:00
|
|
|
// TODO: Optimize
|
2018-02-03 14:28:57 +00:00
|
|
|
code.pxor(tmp, tmp);
|
|
|
|
code.movss(tmp, to_store);
|
|
|
|
code.movaps(addr, tmp);
|
2018-01-26 18:34:22 +00:00
|
|
|
}
|
|
|
|
|
2018-01-21 17:45:43 +00:00
|
|
|
void A64EmitX64::EmitA64SetD(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
const auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-21 17:45:43 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm to_store = ctx.reg_alloc.UseScratchXmm(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(to_store, to_store); // TODO: Remove when able
|
|
|
|
code.movaps(addr, to_store);
|
2018-01-21 17:45:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetQ(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const A64::Vec vec = inst->GetArg(0).GetA64VecRef();
|
|
|
|
const auto addr = xword[r15 + offsetof(A64JitState, vec) + sizeof(u64) * 2 * static_cast<size_t>(vec)];
|
2018-01-21 17:45:43 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[1]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movaps(addr, to_store);
|
2018-01-21 17:45:43 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 11:31:20 +00:00
|
|
|
void A64EmitX64::EmitA64SetSP(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const auto addr = qword[r15 + offsetof(A64JitState, sp)];
|
2018-01-27 00:38:09 +00:00
|
|
|
if (args[0].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[0].GetImmediateS32());
|
2018-01-07 11:31:20 +00:00
|
|
|
} else if (args[0].IsInXmm()) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(addr, to_store);
|
2018-01-07 11:31:20 +00:00
|
|
|
} else {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 to_store = ctx.reg_alloc.UseGpr(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, to_store);
|
2018-01-07 11:31:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-20 17:38:29 +00:00
|
|
|
static void SetFPCRImpl(A64JitState* jit_state, u32 value) {
|
|
|
|
jit_state->SetFpcr(value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetFPCR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0]);
|
|
|
|
code.mov(code.ABI_PARAM1, code.r15);
|
|
|
|
code.CallFunction(SetFPCRImpl);
|
|
|
|
code.ldmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void SetFPSRImpl(A64JitState* jit_state, u32 value) {
|
|
|
|
jit_state->SetFpsr(value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetFPSR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0]);
|
|
|
|
code.mov(code.ABI_PARAM1, code.r15);
|
|
|
|
code.CallFunction(SetFPSRImpl);
|
|
|
|
code.ldmxcsr(code.dword[code.r15 + offsetof(A64JitState, guest_MXCSR)]);
|
|
|
|
}
|
|
|
|
|
2018-07-24 19:04:40 +01:00
|
|
|
void A64EmitX64::EmitA64OrQC(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
|
|
|
|
if (args[0].IsImmediate()) {
|
2019-05-03 17:23:23 +01:00
|
|
|
if (!args[0].GetImmediateU1()) {
|
2018-07-24 19:04:40 +01:00
|
|
|
return;
|
2019-05-03 17:23:23 +01:00
|
|
|
}
|
2018-07-24 19:04:40 +01:00
|
|
|
|
|
|
|
code.mov(code.byte[code.r15 + offsetof(A64JitState, fpsr_qc)], u8(1));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-07-30 10:59:18 +01:00
|
|
|
const Xbyak::Reg8 to_store = ctx.reg_alloc.UseGpr(args[0]).cvt8();
|
2018-07-24 19:04:40 +01:00
|
|
|
code.or_(code.byte[code.r15 + offsetof(A64JitState, fpsr_qc)], to_store);
|
|
|
|
}
|
|
|
|
|
2018-01-07 13:56:32 +00:00
|
|
|
void A64EmitX64::EmitA64SetPC(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const auto addr = qword[r15 + offsetof(A64JitState, pc)];
|
2018-01-27 00:38:09 +00:00
|
|
|
if (args[0].FitsInImmediateS32()) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, args[0].GetImmediateS32());
|
2018-01-07 13:56:32 +00:00
|
|
|
} else if (args[0].IsInXmm()) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Xmm to_store = ctx.reg_alloc.UseXmm(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.movq(addr, to_store);
|
2018-01-07 13:56:32 +00:00
|
|
|
} else {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 to_store = ctx.reg_alloc.UseGpr(args[0]);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(addr, to_store);
|
2018-01-07 13:56:32 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-08 22:03:03 +00:00
|
|
|
void A64EmitX64::EmitA64CallSupervisor(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-01-13 18:00:39 +00:00
|
|
|
ctx.reg_alloc.HostCall(nullptr);
|
2018-01-08 22:03:03 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ASSERT(args[0].IsImmediate());
|
2019-05-03 17:23:23 +01:00
|
|
|
const u32 imm = args[0].GetImmediateU32();
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::CallSVC>(conf.callbacks).EmitCall(code,
|
|
|
|
[&](RegList param) {
|
|
|
|
code.mov(param[0], imm);
|
|
|
|
});
|
2018-06-05 13:05:41 +01:00
|
|
|
// The kernel would have to execute ERET to get here, which would clear exclusive state.
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
2018-01-08 22:03:03 +00:00
|
|
|
}
|
|
|
|
|
2018-01-13 17:54:29 +00:00
|
|
|
void A64EmitX64::EmitA64ExceptionRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
ctx.reg_alloc.HostCall(nullptr);
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ASSERT(args[0].IsImmediate() && args[1].IsImmediate());
|
2019-05-03 17:23:23 +01:00
|
|
|
const u64 pc = args[0].GetImmediateU64();
|
|
|
|
const u64 exception = args[1].GetImmediateU64();
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::ExceptionRaised>(conf.callbacks).EmitCall(code,
|
|
|
|
[&](RegList param) {
|
|
|
|
code.mov(param[0], pc);
|
|
|
|
code.mov(param[1], exception);
|
|
|
|
});
|
2018-01-13 17:54:29 +00:00
|
|
|
}
|
|
|
|
|
2018-02-11 22:53:46 +00:00
|
|
|
void A64EmitX64::EmitA64DataCacheOperationRaised(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, args[0], args[1]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::DataCacheOperationRaised>(conf.callbacks).EmitCall(code);
|
2018-02-11 22:53:46 +00:00
|
|
|
}
|
|
|
|
|
2018-02-11 23:27:28 +00:00
|
|
|
void A64EmitX64::EmitA64DataSynchronizationBarrier(A64EmitContext&, IR::Inst*) {
|
|
|
|
code.mfence();
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64DataMemoryBarrier(A64EmitContext&, IR::Inst*) {
|
|
|
|
code.lfence();
|
|
|
|
}
|
|
|
|
|
2018-08-18 01:20:42 +01:00
|
|
|
void A64EmitX64::EmitA64InstructionSynchronizationBarrier(A64EmitContext& ctx, IR::Inst* ) {
|
|
|
|
ctx.reg_alloc.HostCall(nullptr);
|
|
|
|
|
|
|
|
code.mov(code.ABI_PARAM1, reinterpret_cast<u64>(jit_interface));
|
|
|
|
code.CallFunction(static_cast<void(*)(A64::Jit*)>([](A64::Jit* jit) {
|
|
|
|
jit->ClearCache();
|
|
|
|
}));
|
|
|
|
}
|
|
|
|
|
2018-08-16 09:58:34 +01:00
|
|
|
void A64EmitX64::EmitA64GetCNTFRQ(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-08-16 09:58:34 +01:00
|
|
|
code.mov(result, conf.cntfrq_el0);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-20 16:54:10 +00:00
|
|
|
void A64EmitX64::EmitA64GetCNTPCT(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
ctx.reg_alloc.HostCall(inst);
|
2018-07-22 16:16:26 +01:00
|
|
|
code.UpdateTicks();
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::GetCNTPCT>(conf.callbacks).EmitCall(code);
|
2018-02-20 16:54:10 +00:00
|
|
|
}
|
|
|
|
|
2018-02-20 16:44:13 +00:00
|
|
|
void A64EmitX64::EmitA64GetCTR(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-02-20 16:44:13 +00:00
|
|
|
code.mov(result, conf.ctr_el0);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-12 00:06:44 +00:00
|
|
|
void A64EmitX64::EmitA64GetDCZID(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
|
2018-02-12 00:06:44 +00:00
|
|
|
code.mov(result, conf.dczid_el0);
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-20 17:56:20 +00:00
|
|
|
void A64EmitX64::EmitA64GetTPIDR(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
2018-02-20 17:56:20 +00:00
|
|
|
if (conf.tpidr_el0) {
|
|
|
|
code.mov(result, u64(conf.tpidr_el0));
|
|
|
|
code.mov(result, qword[result]);
|
|
|
|
} else {
|
|
|
|
code.xor_(result.cvt32(), result.cvt32());
|
|
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-02-12 00:06:44 +00:00
|
|
|
void A64EmitX64::EmitA64GetTPIDRRO(A64EmitContext& ctx, IR::Inst* inst) {
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
|
2018-02-12 00:06:44 +00:00
|
|
|
if (conf.tpidrro_el0) {
|
|
|
|
code.mov(result, u64(conf.tpidrro_el0));
|
|
|
|
code.mov(result, qword[result]);
|
|
|
|
} else {
|
|
|
|
code.xor_(result.cvt32(), result.cvt32());
|
|
|
|
}
|
|
|
|
ctx.reg_alloc.DefineValue(inst, result);
|
|
|
|
}
|
|
|
|
|
2018-08-16 09:58:34 +01:00
|
|
|
void A64EmitX64::EmitA64SetTPIDR(A64EmitContext& ctx, IR::Inst* inst) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 value = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
const Xbyak::Reg64 addr = ctx.reg_alloc.ScratchGpr();
|
2018-08-16 09:58:34 +01:00
|
|
|
if (conf.tpidr_el0) {
|
|
|
|
code.mov(addr, u64(conf.tpidr_el0));
|
|
|
|
code.mov(qword[addr], value);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
void A64EmitX64::EmitA64ClearExclusive(A64EmitContext&, IR::Inst*) {
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64SetExclusive(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:27:37 +01:00
|
|
|
if (conf.global_monitor) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
|
|
|
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(1));
|
|
|
|
code.mov(code.ABI_PARAM1, reinterpret_cast<u64>(&conf));
|
|
|
|
code.CallFunction(static_cast<void(*)(A64::UserConfig&, u64, u8)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u8 size) {
|
|
|
|
conf.global_monitor->Mark(conf.processor_id, vaddr, size);
|
|
|
|
}
|
|
|
|
));
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ASSERT(args[1].IsImmediate());
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 address = ctx.reg_alloc.UseGpr(args[0]);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(1));
|
2018-02-13 14:02:59 +00:00
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, exclusive_address)], address);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
2018-10-14 22:17:56 +01:00
|
|
|
static Xbyak::RegExp EmitVAddrLookup(BlockOfCode& code, A64EmitContext& ctx, Xbyak::Label& abort, Xbyak::Reg64 vaddr, std::optional<Xbyak::Reg64> arg_scratch = {}) {
|
2018-09-22 18:54:49 +01:00
|
|
|
constexpr size_t page_bits = 12;
|
|
|
|
constexpr size_t page_size = 1 << page_bits;
|
|
|
|
const size_t valid_page_index_bits = ctx.conf.page_table_address_space_bits - page_bits;
|
2018-02-18 13:00:41 +00:00
|
|
|
const size_t unused_top_bits = 64 - ctx.conf.page_table_address_space_bits;
|
2018-02-12 19:49:56 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 page_table = arg_scratch ? *arg_scratch : ctx.reg_alloc.ScratchGpr();
|
|
|
|
const Xbyak::Reg64 tmp = ctx.reg_alloc.ScratchGpr();
|
2018-02-18 13:00:41 +00:00
|
|
|
code.mov(page_table, reinterpret_cast<u64>(ctx.conf.page_table));
|
2018-02-12 19:49:56 +00:00
|
|
|
code.mov(tmp, vaddr);
|
2018-02-12 20:49:52 +00:00
|
|
|
if (unused_top_bits == 0) {
|
2018-09-22 18:54:49 +01:00
|
|
|
code.shr(tmp, int(page_bits));
|
2018-02-18 13:00:41 +00:00
|
|
|
} else if (ctx.conf.silently_mirror_page_table) {
|
2018-02-12 20:49:52 +00:00
|
|
|
if (valid_page_index_bits >= 32) {
|
|
|
|
code.shl(tmp, int(unused_top_bits));
|
2018-09-22 18:54:49 +01:00
|
|
|
code.shr(tmp, int(unused_top_bits + page_bits));
|
2018-02-12 20:49:52 +00:00
|
|
|
} else {
|
2018-09-22 18:54:49 +01:00
|
|
|
code.shr(tmp, int(page_bits));
|
2018-02-12 20:49:52 +00:00
|
|
|
code.and_(tmp, u32((1 << valid_page_index_bits) - 1));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ASSERT(valid_page_index_bits < 32);
|
2018-09-22 18:54:49 +01:00
|
|
|
code.shr(tmp, int(page_bits));
|
2018-02-12 20:49:52 +00:00
|
|
|
code.test(tmp, u32(-(1 << valid_page_index_bits)));
|
|
|
|
code.jnz(abort, code.T_NEAR);
|
|
|
|
}
|
2018-02-12 19:49:56 +00:00
|
|
|
code.mov(page_table, qword[page_table + tmp * sizeof(void*)]);
|
2018-02-12 20:49:52 +00:00
|
|
|
code.test(page_table, page_table);
|
|
|
|
code.jz(abort, code.T_NEAR);
|
2018-02-12 19:49:56 +00:00
|
|
|
code.mov(tmp, vaddr);
|
2018-09-22 18:54:49 +01:00
|
|
|
code.and_(tmp, static_cast<u32>(page_size - 1));
|
2018-02-12 20:49:52 +00:00
|
|
|
return page_table + tmp;
|
2018-02-12 19:49:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitDirectPageTableMemoryRead(A64EmitContext& ctx, IR::Inst* inst, size_t bitsize) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
const Xbyak::Reg64 value = ctx.reg_alloc.ScratchGpr();
|
2018-02-12 19:49:56 +00:00
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
auto src_ptr = EmitVAddrLookup(code, ctx, abort, vaddr, value);
|
2018-02-12 19:49:56 +00:00
|
|
|
switch (bitsize) {
|
|
|
|
case 8:
|
|
|
|
code.movzx(value.cvt32(), code.byte[src_ptr]);
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
code.movzx(value.cvt32(), word[src_ptr]);
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
code.mov(value.cvt32(), dword[src_ptr]);
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
code.mov(value, qword[src_ptr]);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(read_fallbacks[std::make_tuple(bitsize, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
|
|
|
|
ctx.reg_alloc.DefineValue(inst, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitDirectPageTableMemoryWrite(A64EmitContext& ctx, IR::Inst* inst, size_t bitsize) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
const Xbyak::Reg64 value = ctx.reg_alloc.UseGpr(args[1]);
|
2018-02-12 19:49:56 +00:00
|
|
|
|
2018-02-18 13:00:41 +00:00
|
|
|
auto dest_ptr = EmitVAddrLookup(code, ctx, abort, vaddr);
|
2018-02-12 19:49:56 +00:00
|
|
|
switch (bitsize) {
|
|
|
|
case 8:
|
|
|
|
code.mov(code.byte[dest_ptr], value.cvt8());
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
code.mov(word[dest_ptr], value.cvt16());
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
code.mov(dword[dest_ptr], value.cvt32());
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
code.mov(qword[dest_ptr], value);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(write_fallbacks[std::make_tuple(bitsize, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
}
|
|
|
|
|
2018-01-10 01:13:23 +00:00
|
|
|
void A64EmitX64::EmitA64ReadMemory8(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 8);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryRead8>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ReadMemory16(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 16);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryRead16>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ReadMemory32(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 32);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryRead32>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ReadMemory64(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryRead(ctx, inst, 64);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryRead64>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
2018-01-24 15:55:59 +00:00
|
|
|
void A64EmitX64::EmitA64ReadMemory128(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
const Xbyak::Xmm value = ctx.reg_alloc.ScratchXmm();
|
2018-02-12 19:49:56 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const auto src_ptr = EmitVAddrLookup(code, ctx, abort, vaddr);
|
2018-02-12 20:49:52 +00:00
|
|
|
code.movups(value, xword[src_ptr]);
|
2018-02-12 19:49:56 +00:00
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(read_fallbacks[std::make_tuple(128, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
|
|
|
|
ctx.reg_alloc.DefineValue(inst, value);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0]);
|
2018-02-12 18:18:47 +00:00
|
|
|
code.CallFunction(memory_read_128);
|
2018-07-31 20:53:33 +01:00
|
|
|
ctx.reg_alloc.DefineValue(inst, xmm1);
|
2018-01-24 15:55:59 +00:00
|
|
|
}
|
|
|
|
|
2018-01-10 01:13:23 +00:00
|
|
|
void A64EmitX64::EmitA64WriteMemory8(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 8);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryWrite8>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64WriteMemory16(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 16);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryWrite16>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64WriteMemory32(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 32);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryWrite32>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64WriteMemory64(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
EmitDirectPageTableMemoryWrite(ctx, inst, 64);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.HostCall(nullptr, {}, args[0], args[1]);
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::MemoryWrite64>(conf.callbacks).EmitCall(code);
|
2018-01-10 01:13:23 +00:00
|
|
|
}
|
|
|
|
|
2018-01-24 15:55:59 +00:00
|
|
|
void A64EmitX64::EmitA64WriteMemory128(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-02-12 19:49:56 +00:00
|
|
|
if (conf.page_table) {
|
|
|
|
Xbyak::Label abort, end;
|
|
|
|
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
const Xbyak::Xmm value = ctx.reg_alloc.UseXmm(args[1]);
|
2018-02-12 19:49:56 +00:00
|
|
|
|
2019-05-03 17:23:23 +01:00
|
|
|
const auto dest_ptr = EmitVAddrLookup(code, ctx, abort, vaddr);
|
2018-02-12 19:49:56 +00:00
|
|
|
code.movups(xword[dest_ptr], value);
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
code.SwitchToFarCode();
|
|
|
|
code.L(abort);
|
|
|
|
code.call(write_fallbacks[std::make_tuple(128, vaddr.getIdx(), value.getIdx())]);
|
|
|
|
code.jmp(end, code.T_NEAR);
|
|
|
|
code.SwitchToNearCode();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-02-09 15:58:16 +00:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
ctx.reg_alloc.Use(args[0], ABI_PARAM2);
|
2018-07-31 20:53:33 +01:00
|
|
|
ctx.reg_alloc.Use(args[1], HostLoc::XMM1);
|
2018-02-09 15:58:16 +00:00
|
|
|
ctx.reg_alloc.EndOfAllocScope();
|
|
|
|
ctx.reg_alloc.HostCall(nullptr);
|
2018-02-12 18:18:47 +00:00
|
|
|
code.CallFunction(memory_write_128);
|
2018-01-24 15:55:59 +00:00
|
|
|
}
|
|
|
|
|
2018-06-05 12:26:05 +01:00
|
|
|
void A64EmitX64::EmitExclusiveWrite(A64EmitContext& ctx, IR::Inst* inst, size_t bitsize) {
|
2018-06-05 12:27:37 +01:00
|
|
|
if (conf.global_monitor) {
|
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
|
|
|
|
|
|
|
if (bitsize != 128) {
|
|
|
|
ctx.reg_alloc.HostCall(inst, {}, args[0], args[1]);
|
|
|
|
} else {
|
|
|
|
ctx.reg_alloc.Use(args[0], ABI_PARAM2);
|
2018-07-31 20:53:33 +01:00
|
|
|
ctx.reg_alloc.Use(args[1], HostLoc::XMM1);
|
2018-06-05 12:27:37 +01:00
|
|
|
ctx.reg_alloc.EndOfAllocScope();
|
|
|
|
ctx.reg_alloc.HostCall(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
Xbyak::Label end;
|
|
|
|
|
|
|
|
code.mov(code.ABI_RETURN, u32(1));
|
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
code.je(end);
|
|
|
|
code.mov(code.ABI_PARAM1, reinterpret_cast<u64>(&conf));
|
|
|
|
switch (bitsize) {
|
|
|
|
case 8:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u8)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u8 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 1, [&]{
|
|
|
|
conf.callbacks->MemoryWrite8(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u16)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u16 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 2, [&]{
|
|
|
|
conf.callbacks->MemoryWrite16(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u32)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u32 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 4, [&]{
|
|
|
|
conf.callbacks->MemoryWrite32(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 64:
|
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, u64)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, u64 value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 8, [&]{
|
|
|
|
conf.callbacks->MemoryWrite64(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
|
|
|
break;
|
|
|
|
case 128:
|
2018-07-22 15:05:53 +01:00
|
|
|
code.sub(rsp, 16 + ABI_SHADOW_SPACE);
|
2018-06-05 12:27:37 +01:00
|
|
|
code.lea(code.ABI_PARAM3, ptr[rsp + ABI_SHADOW_SPACE]);
|
2018-07-31 20:53:33 +01:00
|
|
|
code.movaps(xword[code.ABI_PARAM3], xmm1);
|
2018-06-05 12:27:37 +01:00
|
|
|
code.CallFunction(static_cast<u32(*)(A64::UserConfig&, u64, A64::Vector&)>(
|
|
|
|
[](A64::UserConfig& conf, u64 vaddr, A64::Vector& value) -> u32 {
|
|
|
|
return conf.global_monitor->DoExclusiveOperation(conf.processor_id, vaddr, 16, [&]{
|
|
|
|
conf.callbacks->MemoryWrite128(vaddr, value);
|
|
|
|
}) ? 0 : 1;
|
|
|
|
}
|
|
|
|
));
|
2018-07-22 15:05:53 +01:00
|
|
|
code.add(rsp, 16 + ABI_SHADOW_SPACE);
|
2018-06-05 12:27:37 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
}
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-06-05 12:26:05 +01:00
|
|
|
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg64 vaddr = ctx.reg_alloc.UseGpr(args[0]);
|
|
|
|
const int value_idx = bitsize != 128
|
|
|
|
? ctx.reg_alloc.UseGpr(args[1]).getIdx()
|
|
|
|
: ctx.reg_alloc.UseXmm(args[1]).getIdx();
|
2018-06-05 12:26:05 +01:00
|
|
|
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
Xbyak::Label end;
|
2019-05-03 17:23:23 +01:00
|
|
|
const Xbyak::Reg32 passed = ctx.reg_alloc.ScratchGpr().cvt32();
|
|
|
|
const Xbyak::Reg64 tmp = ctx.reg_alloc.ScratchGpr();
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
|
|
|
|
code.mov(passed, u32(1));
|
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
code.je(end);
|
|
|
|
code.mov(tmp, vaddr);
|
2018-02-13 14:02:59 +00:00
|
|
|
code.xor_(tmp, qword[r15 + offsetof(A64JitState, exclusive_address)]);
|
|
|
|
code.test(tmp, static_cast<u32>(A64JitState::RESERVATION_GRANULE_MASK & 0xFFFF'FFFF));
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
code.jne(end);
|
|
|
|
code.mov(code.byte[r15 + offsetof(A64JitState, exclusive_state)], u8(0));
|
|
|
|
code.call(write_fallbacks[std::make_tuple(bitsize, vaddr.getIdx(), value_idx)]);
|
|
|
|
code.xor_(passed, passed);
|
|
|
|
code.L(end);
|
|
|
|
|
|
|
|
ctx.reg_alloc.DefineValue(inst, passed);
|
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory8(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 8);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory16(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 16);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory32(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 32);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory64(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 64);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitA64ExclusiveWriteMemory128(A64EmitContext& ctx, IR::Inst* inst) {
|
2018-06-05 12:26:05 +01:00
|
|
|
EmitExclusiveWrite(ctx, inst, 128);
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
|
|
|
}
|
|
|
|
|
2018-07-27 12:42:10 +01:00
|
|
|
std::string A64EmitX64::LocationDescriptorToFriendlyName(const IR::LocationDescriptor& ir_descriptor) const {
|
|
|
|
const A64::LocationDescriptor descriptor{ir_descriptor};
|
|
|
|
return fmt::format("a64_{:016X}_fpcr{:08X}",
|
|
|
|
descriptor.PC(),
|
|
|
|
descriptor.FPCR().Value());
|
|
|
|
}
|
|
|
|
|
2018-01-06 21:15:25 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::Interpret terminal, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.SwitchMxcsrOnExit();
|
2018-08-03 09:09:29 +01:00
|
|
|
Devirtualize<&A64::UserCallbacks::InterpreterFallback>(conf.callbacks).EmitCall(code,
|
|
|
|
[&](RegList param) {
|
|
|
|
code.mov(param[0], A64::LocationDescriptor{terminal.next}.PC());
|
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, pc)], param[0]);
|
|
|
|
code.mov(param[1].cvt32(), terminal.num_instructions);
|
|
|
|
});
|
2018-02-03 14:28:57 +00:00
|
|
|
code.ReturnFromRunCode(true); // TODO: Check cycles
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::ReturnToDispatch, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.ReturnFromRunCode();
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::LinkBlock terminal, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.cmp(qword[r15 + offsetof(A64JitState, cycles_remaining)], 0);
|
2018-01-06 21:15:25 +00:00
|
|
|
|
2018-02-03 14:28:57 +00:00
|
|
|
patch_information[terminal.next].jg.emplace_back(code.getCurr());
|
2018-01-06 21:15:25 +00:00
|
|
|
if (auto next_bb = GetBasicBlock(terminal.next)) {
|
|
|
|
EmitPatchJg(terminal.next, next_bb->entrypoint);
|
|
|
|
} else {
|
|
|
|
EmitPatchJg(terminal.next);
|
|
|
|
}
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(rax, A64::LocationDescriptor{terminal.next}.PC());
|
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, pc)], rax);
|
|
|
|
code.ForceReturnFromRunCode();
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::LinkBlockFast terminal, IR::LocationDescriptor) {
|
2018-02-03 14:28:57 +00:00
|
|
|
patch_information[terminal.next].jmp.emplace_back(code.getCurr());
|
2018-01-06 21:15:25 +00:00
|
|
|
if (auto next_bb = GetBasicBlock(terminal.next)) {
|
|
|
|
EmitPatchJmp(terminal.next, next_bb->entrypoint);
|
|
|
|
} else {
|
|
|
|
EmitPatchJmp(terminal.next);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-27 22:44:17 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::PopRSBHint, IR::LocationDescriptor) {
|
2018-09-07 21:51:42 +01:00
|
|
|
code.jmp(terminal_handler_pop_rsb_hint);
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-09-07 21:51:42 +01:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::FastDispatchHint, IR::LocationDescriptor) {
|
|
|
|
if (conf.enable_fast_dispatch) {
|
|
|
|
code.jmp(terminal_handler_fast_dispatch_hint);
|
|
|
|
} else {
|
|
|
|
code.ReturnFromRunCode();
|
|
|
|
}
|
2018-09-07 21:29:47 +01:00
|
|
|
}
|
|
|
|
|
2018-01-06 21:15:25 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::If terminal, IR::LocationDescriptor initial_location) {
|
2018-01-17 00:34:33 +00:00
|
|
|
switch (terminal.if_) {
|
|
|
|
case IR::Cond::AL:
|
|
|
|
case IR::Cond::NV:
|
|
|
|
EmitTerminal(terminal.then_, initial_location);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
Xbyak::Label pass = EmitCond(terminal.if_);
|
|
|
|
EmitTerminal(terminal.else_, initial_location);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.L(pass);
|
2018-01-17 00:34:33 +00:00
|
|
|
EmitTerminal(terminal.then_, initial_location);
|
|
|
|
break;
|
|
|
|
}
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 16:33:02 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::CheckBit terminal, IR::LocationDescriptor initial_location) {
|
|
|
|
Xbyak::Label fail;
|
2018-02-03 14:28:57 +00:00
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, check_bit)], u8(0));
|
|
|
|
code.jz(fail);
|
2018-01-07 16:33:02 +00:00
|
|
|
EmitTerminal(terminal.then_, initial_location);
|
2018-02-03 14:28:57 +00:00
|
|
|
code.L(fail);
|
2018-01-07 16:33:02 +00:00
|
|
|
EmitTerminal(terminal.else_, initial_location);
|
|
|
|
}
|
|
|
|
|
2018-01-06 21:15:25 +00:00
|
|
|
void A64EmitX64::EmitTerminalImpl(IR::Term::CheckHalt terminal, IR::LocationDescriptor initial_location) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.cmp(code.byte[r15 + offsetof(A64JitState, halt_requested)], u8(0));
|
|
|
|
code.jne(code.GetForceReturnFromRunCodeAddress());
|
2018-01-06 21:15:25 +00:00
|
|
|
EmitTerminal(terminal.else_, initial_location);
|
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
|
|
void A64EmitX64::EmitPatchJg(const IR::LocationDescriptor& target_desc, CodePtr target_code_ptr) {
|
2018-02-03 14:28:57 +00:00
|
|
|
const CodePtr patch_location = code.getCurr();
|
2018-01-06 21:15:25 +00:00
|
|
|
if (target_code_ptr) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.jg(target_code_ptr);
|
2018-01-06 21:15:25 +00:00
|
|
|
} else {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(rax, A64::LocationDescriptor{target_desc}.PC());
|
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, pc)], rax);
|
|
|
|
code.jg(code.GetReturnFromRunCodeAddress());
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
2018-02-03 14:28:57 +00:00
|
|
|
code.EnsurePatchLocationSize(patch_location, 30); // TODO: Reduce size
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-01-07 00:11:57 +00:00
|
|
|
void A64EmitX64::EmitPatchJmp(const IR::LocationDescriptor& target_desc, CodePtr target_code_ptr) {
|
2018-02-03 14:28:57 +00:00
|
|
|
const CodePtr patch_location = code.getCurr();
|
2018-01-06 21:15:25 +00:00
|
|
|
if (target_code_ptr) {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.jmp(target_code_ptr);
|
2018-01-06 21:15:25 +00:00
|
|
|
} else {
|
2018-02-03 14:28:57 +00:00
|
|
|
code.mov(rax, A64::LocationDescriptor{target_desc}.PC());
|
|
|
|
code.mov(qword[r15 + offsetof(A64JitState, pc)], rax);
|
|
|
|
code.jmp(code.GetReturnFromRunCodeAddress());
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
2018-02-03 14:28:57 +00:00
|
|
|
code.EnsurePatchLocationSize(patch_location, 30); // TODO: Reduce size
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void A64EmitX64::EmitPatchMovRcx(CodePtr target_code_ptr) {
|
|
|
|
if (!target_code_ptr) {
|
2018-02-03 14:28:57 +00:00
|
|
|
target_code_ptr = code.GetReturnFromRunCodeAddress();
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
2018-02-03 14:28:57 +00:00
|
|
|
const CodePtr patch_location = code.getCurr();
|
|
|
|
code.mov(code.rcx, reinterpret_cast<u64>(target_code_ptr));
|
|
|
|
code.EnsurePatchLocationSize(patch_location, 10);
|
2018-01-06 21:15:25 +00:00
|
|
|
}
|
|
|
|
|
2018-01-26 13:51:48 +00:00
|
|
|
} // namespace Dynarmic::BackendX64
|