Lioncash
a8ba15f0d5
intrusive_list: Make Remove and IsEmpty stdlib compatible
...
Makes the name match the standard library equivalents.
C++17 introduces non-member empty() which allows for nicer handling
in generic contexts. May as well make the data structure compatible with
it.
2016-08-19 20:25:18 +01:00
Lioncash
23d190f7b0
intrusive_list: Support inserters
...
Allows std::inserter, std::back_inserter, and std::front_inserter to work
with intrusive lists.
2016-08-19 20:25:17 +01:00
Lioncash
36a0ad5bc2
reg_alloc: const correctness for ValueLocation()
2016-08-19 19:33:57 +01:00
MerryMage
2d6a86e43c
Remove <cassert>
2016-08-19 01:53:24 +01:00
MerryMage
192a0029be
ir/opcodes: Implement IR::AreTypesCompatible
...
Type-checking is now occuring in more than one place.
2016-08-19 01:34:14 +01:00
Tillmann Karras
9782e7da3f
verification_pass: show type errors
2016-08-19 01:17:30 +01:00
Tillmann Karras
dad7724b86
TranlateArm: implement remaining multiplies
...
SMLALxy, SMLAxy, SMULxy SMLAWy, SMULWy, SMLAD, SMLALD, SMLSD, SMLSLD,
SMUAD, SMUSD
2016-08-19 01:08:38 +01:00
MerryMage
fe15cbd50e
translate_arm/parallel: Detect UNPREDICTABLE instructions
2016-08-19 00:59:07 +01:00
MerryMage
2119dfc926
translate_arm/multiply: MLA is UNPREDICTABLE when Ra == R15
2016-08-19 00:59:05 +01:00
MerryMage
0d0f4b1b4f
translate_arm/load_store: Correct implementation for LDM*
2016-08-19 00:59:04 +01:00
MerryMage
4acc481463
translate_arm/load_store: Handle unpredictable instructions
...
This necessated handling literal versions of the instructions separately
as they had different requirements. The rationale for detecting
unpredictable instructions is because:
a. they are unlikely to be outputted by a well-behaved compiler
b. their behaviour may change between different processors
I would rather unpredictable instructions fail loudly than silently do
approximately the right thing.
2016-08-19 00:59:02 +01:00
MerryMage
5869e79b9c
translate_arm: Simplify EmitImmShift and EmitRegShift
2016-08-19 00:21:31 +01:00
Lioncash
fe9329ef3e
intrusive_list: Add list class type definitions; extend iterator interface
...
Adds type definitions, and extends the list interface to support all
standard library forms of iterator creation.
2016-08-18 23:47:26 +01:00
Lioncash
95a83543f2
intrusive_list: Get rid of unnecessary static_casts
...
The only valid objects to add to the list are those that inherit from
IntrusiveListNode. Therefore anything being added to the list that isn't
inheriting from it will cause compilation to fail.
2016-08-18 23:47:26 +01:00
Lioncash
67509935f6
intrusive_list: Eliminate need for separate const iterator construct
...
This generalizes the regular iterator to be compatible with both use
cases. Passing in the list instance directly isn't needed, because the
only way you'd ever get a valid instantiation of an iterator is from a
list instance itself.
2016-08-18 23:47:26 +01:00
MerryMage
b8cf43c43e
translate_arm/data_processing: Rd == R15 is unpredictable for rsr instructions
2016-08-18 18:23:05 +01:00
MerryMage
efc8d2f772
arm_translator: NV conditional is obsolete
2016-08-18 18:21:48 +01:00
MerryMage
5f7d940fde
disassemble_arm: Partially implement coprocessor and hint instructions
2016-08-18 18:21:16 +01:00
MerryMage
36a916a766
decoder/arm: Correct NOP decoder
2016-08-18 18:20:29 +01:00
MerryMage
e9e7ac6e65
decoder/arm: Correct PLD decoder for v6K
2016-08-18 18:19:34 +01:00
MerryMage
269160ef0d
emit_x64: Clear RSB-related caches when ClearCache() is called
2016-08-18 18:18:44 +01:00
MerryMage
1a3f3ac435
emit_x64: Correct behaviour of PackedOperation for immediate argument
...
x64 MOVD_xmm does not support an immediate oparg
2016-08-18 18:17:17 +01:00
MerryMage
b2de47954b
EmitX64: Emit correct cycle count on cond failure
2016-08-18 18:16:18 +01:00
Lioncash
841098a0bc
ir: separate components out a little more
2016-08-17 20:46:21 +01:00
Lioncash
9690d1423d
intrusive_list: explicitly default relevant constructors
2016-08-17 20:46:11 +01:00
Lioncash
cbd99e4367
jitstate: Use std::array's fill() in ResetRSB
...
Performs the equivalent behavior
2016-08-17 10:10:43 +01:00
Lioncash
74ee92ee38
jitstate: const correctness
...
GetReturnFromRunCodeAddress is const qualified, so this can accept a const
pointer. This also allows for making the constructor accept a const
pointer as well.
2016-08-17 10:10:43 +01:00
Lioncash
9ed9f4c565
mp: Generalize function information retrieval
...
Generalizes MemFnInfo to be compatible with all function types.
Also adds type introspection for arguments, as well as helper templates for the common types supported by all partial specializations.
2016-08-17 10:08:40 +01:00
Lioncash
439619c827
reg_alloc: Make GetRegLoc return by const reference
...
Considering a HostLocInfo instance houses a std::vector, every time this
function is called can cause a potential heap allocation.
This can be somewhat unnecessary because this function is only used to query
for information we already have.
Considering this is used by several other internal query functions such as
IsRegisterOccupied, IsRegisterAllocated, and IsLastUse, this will result
in better codegen (returning an address is just 3 instructions excluding
the ret instruction for returning, meanwhile heap alloc can be 60+).
This also renames the function to have the same name as its non-const
counterpart, since overloading will just select the correct function
instead of putting that onus on the developer.
2016-08-17 10:08:08 +01:00
MerryMage
0ebb572e2d
Optimization: Make RSB a ring buffer instead of a stack
2016-08-15 15:48:22 +01:00
MerryMage
7d7ac0af71
Optimization: Make SVC use RSB
2016-08-15 15:02:08 +01:00
MerryMage
6c45619aa1
Optimization: Implement terminal LinkBlockFast
2016-08-15 14:33:17 +01:00
MerryMage
624e84fa09
Optimization: Tweak RSB
2016-08-15 14:08:06 +01:00
MerryMage
070298b948
Optimization: bugfix! Return Stack Buffer location hash calculation was incorrect
2016-08-15 13:21:58 +01:00
MerryMage
e164ede4dc
TranslateArm: Implement MRS, MSR (imm), MSR (reg)
2016-08-15 11:50:49 +01:00
bunnei
30f3d869cc
TranslateArm: Implement VPUSH and VPOP.
2016-08-13 19:37:03 +01:00
MerryMage
9c82a12f8f
ir_opt: Update VerificationPass to current IR
2016-08-13 18:39:49 +01:00
MerryMage
8fc21f481a
RegAlloc: Handle case when def is unused
2016-08-13 01:55:03 +01:00
MerryMage
d43d97b990
EmitX64/EmitPushRSB: Assert that patch location is of correct size
2016-08-13 00:52:31 +01:00
MerryMage
960d14d18e
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9
TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16.
2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032
TranslateArm: Implement QADD8 and UQADD8.
2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb
TranslateArm: Implement QSUB8.
2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2
TranslateArm: Implement UQSUB8.
2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce
Update documentation (2016-08-12)
2016-08-12 18:17:31 +01:00
MerryMage
3808938c98
Fix SETEND
2016-08-11 19:15:58 +01:00
bunnei
218980cf69
load_store: Implement LDRSB and LDRSH.
2016-08-11 17:18:20 +01:00
MerryMage
0e5593ba62
TranslateArm: Implement SETEND
2016-08-11 17:15:33 +01:00
MerryMage
8964b38cf9
IR/DumpBlock: Print references to ExtRegs
2016-08-11 17:15:02 +01:00
MerryMage
b4c586d5ef
TranslateArm: VSTR: Correct behaviour in big-endian mode
2016-08-10 16:43:37 +01:00
MerryMage
945498a16a
DisassemblerArm: Disassemble SETEND
2016-08-10 16:15:07 +01:00
bunnei
8e8db6e137
TranslateArm: Implement VSTR.
2016-08-10 15:01:23 +01:00
MerryMage
df39308e03
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:57:20 +01:00
MerryMage
d921390928
TranslateArm: Add santity check to see if we've emitted a terminal instruction
2016-08-09 22:47:41 +01:00
MerryMage
2eec43178a
IR: Opaque can be of any type
2016-08-09 22:46:44 +01:00
MerryMage
29d30bf931
Interface: Added Jit::Reset to reset CPU state
2016-08-09 22:45:54 +01:00
MerryMage
82f42d065f
DisassemblerArm: Implemented disassembly of STR*/LDR* instructions
2016-08-09 22:44:42 +01:00
MerryMage
d0d51ba346
TranslateArm: Implement STM, STMDA, STMDB, STMIB
2016-08-08 22:49:11 +01:00
Tillmann Karras
5d26899ac9
Add simplified LogicalShiftRight64 IR opcode
2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5
Add support for the APSR.Q flag
2016-08-08 22:27:04 +01:00
Tillmann Karras
11e0688e5f
Fix build on case-sensitive file systems
2016-08-08 22:27:03 +01:00
MerryMage
85549d7ae2
TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB
2016-08-08 22:26:06 +01:00
MerryMage
46e4864707
ArmTypes: Add RegListToString and reorganise
2016-08-08 22:20:28 +01:00
MerryMage
975f011fc0
BackendX64/RegAlloc: Do not allocate RSP for guest use
2016-08-08 16:01:07 +01:00
MerryMage
abd113f160
EmitX64: Renamed patch_jmp_locations to patch_jg_locations
2016-08-08 15:56:07 +01:00
MerryMage
52fa998e6b
EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags
2016-08-07 22:47:43 +01:00
MerryMage
04c1a0d2de
EmitX64: Switch MXCSR when switching to interpreter
2016-08-07 22:47:17 +01:00
MerryMage
edb236ab07
Correct implementation of thumb16_SVC and arm_SVC
2016-08-07 22:19:39 +01:00
MerryMage
a32063fa60
EmitX64: Implement block linking
2016-08-07 22:11:39 +01:00
MerryMage
328422b740
RegAlloc: HostCall flushes all XMM regsiters
2016-08-07 21:02:16 +01:00
MerryMage
4dcd1d1859
Arm: BLX is UNPREDICTABLE when Rm is PC
2016-08-07 20:50:33 +01:00
MerryMage
1af5bef32c
TranslateArm: Implement BLX (imm), BLX (reg) and BXJ
2016-08-07 20:40:31 +01:00
MerryMage
939bb5c0cb
TranslateArm: Implement NOP
2016-08-07 20:08:31 +01:00
MerryMage
e48df9d8fd
TranslateArm: Implement Hint instructions as NOPs
2016-08-07 20:04:48 +01:00
MerryMage
3a465ba4a8
VFP: Implement VLDR
2016-08-07 19:59:35 +01:00
MerryMage
a2c2db277b
VFP: Implement VMOV (all variants)
2016-08-07 19:25:12 +01:00
MerryMage
aba705f6b9
BackendX64: Merge Routines into BlockOfCode
2016-08-07 18:08:48 +01:00
MerryMage
0f412247ed
VFP: Implement VSQRT
2016-08-07 12:19:07 +01:00
MerryMage
cd8e7c0504
VFP: Implement VNEG
2016-08-07 12:04:21 +01:00
MerryMage
da33af5abe
VFP: Implement VMLA, VMLS, VNMLA, VNMLS
2016-08-07 11:49:06 +01:00
MerryMage
3f1345a1a5
VFP: Implement VNMUL, VDIV
2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359
VFP: Implement VMUL
2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f
VFP: Implement VSUB
2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210
VFP: Implement VABS
2016-08-07 01:27:18 +01:00
MerryMage
f88b1b4c2e
FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask
2016-08-07 01:10:19 +01:00
MerryMage
c35f06470f
VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1
2016-08-06 23:01:18 +01:00
MerryMage
94b99f5949
Common: Add an intrusive list implementation; remove use of boost::intrusive::list.
2016-08-06 22:23:01 +01:00
Tillmann Karras
9264e2e04c
Use XOR when loading a zero immediate
2016-08-06 21:17:11 +01:00
Tillmann Karras
55204a80d0
Implement SMMLA, SMMLS, SMMUL
2016-08-06 21:17:11 +01:00
Tillmann Karras
846d07d7b5
Add Sub64 opcode
2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f
Add carry support to MostSignificantWord
2016-08-06 21:17:11 +01:00
Tillmann Karras
01aebcb385
Remove *MulHi wrappers
2016-08-06 21:17:11 +01:00
Tillmann Karras
5e047107a0
Disassemble more instructions
...
CLZ, SEL, USAD8, USADA8, SSAT, SSAT16, USAT, USAT16, SMLAL*, SMLA*,
SMUL*, SMLAW*, SMULW*, SMLAD, SMLALD, SMLSD, SMLSLD, SMUAD, SMUSD
2016-08-06 21:17:11 +01:00
Tillmann Karras
f99cb613cf
Disassemble packs and more multiplies
2016-08-06 21:17:11 +01:00
MerryMage
7915f97d98
TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning)
2016-08-06 20:42:06 +01:00
MerryMage
4d127c19dd
Common: Add a memory pool implementation, remove use of boost::pool
2016-08-06 20:41:00 +01:00
MerryMage
411e804b0d
Interface: Forward declare Arm::LocationDescriptor
2016-08-06 20:11:35 +01:00
MerryMage
4b31ea25a7
VFP: Implement VADD.{F32,F64}
2016-08-06 20:03:15 +01:00
MerryMage
8ff414ee0e
Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top.
2016-08-06 20:03:15 +01:00
MerryMage
94d5738f62
BackendX64/Routines: Add floating-point constants
2016-08-06 20:01:47 +01:00
MerryMage
8754728a82
BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case
2016-08-06 20:01:47 +01:00
MerryMage
8cc4fe8a10
BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly
2016-08-06 20:01:47 +01:00
bunnei
2448d52394
load_store: Use correct types for LDR/STR.
2016-08-05 20:51:32 -04:00
bunnei
8c2300d477
arm: Implement LDRD reg/imm instructions.
2016-08-05 20:05:02 -04:00
bunnei
72608b7af6
arm: Handle Cond::NV (some 3DS games use this despite being obsolete).
2016-08-05 20:05:02 -04:00
bunnei
ec3a98cf95
arm: Implement LDRH reg/imm instructions.
2016-08-05 20:05:01 -04:00
bunnei
192a0fba7a
arm: Implement LDRB reg/imm instructions.
2016-08-05 20:05:00 -04:00
bunnei
dfb318f208
arm: Implement STRD reg/imm instructions.
2016-08-05 20:04:59 -04:00
bunnei
e931dc2496
arm: Implement STRH reg/imm instructions.
2016-08-05 20:04:58 -04:00
bunnei
9f77662b24
arm: Implement STRB reg/imm instructions.
2016-08-05 20:04:57 -04:00
bunnei
caab1bbc7c
arm: Implement STR reg/imm instructions.
2016-08-05 20:04:56 -04:00
bunnei
b09ecb4532
arm: Implement LDR reg/imm instructions.
2016-08-05 20:04:55 -04:00
MerryMage
856298577d
EmitX64: Don't give MOVSX or MOVZX an immediate oparg
2016-08-06 01:03:39 +01:00
MerryMage
640ce48baa
VFP: Implement {Get,Set}ExtendedRegister{32,64}
2016-08-05 19:06:10 +01:00
MerryMage
d31bbd6d14
Common/x64/CpuDetect: Disable MSVC warning for strncpy
2016-08-05 18:44:01 +01:00
MerryMage
4c0a85f3b3
EmitX64: Correct EmitPack2x32To1x64 implementation
2016-08-05 18:43:24 +01:00
MerryMage
742eeb8913
BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations
2016-08-05 18:43:22 +01:00
MerryMage
d2aeb56503
Common: DEBUG_ASSERTs weren't enabled
2016-08-05 18:43:21 +01:00
MerryMage
d80dcc5367
BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64
2016-08-05 15:27:29 +01:00
MerryMage
2b025183a2
BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use
2016-08-05 15:24:25 +01:00
MerryMage
b4aa01ccf4
Merge remote-tracking branch 'tilkax/master'
2016-08-05 14:14:06 +01:00
MerryMage
94e75ad32f
BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg}
2016-08-05 14:11:27 +01:00
MerryMage
92bd5f214b
BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg
2016-08-05 14:10:39 +01:00
MerryMage
01cfaf0286
IR: Properly support Identity in IR::Value
2016-08-05 14:09:10 +01:00
MerryMage
ca40015145
IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint)
2016-08-05 14:07:27 +01:00
Tillmann Karras
fce8c86c90
Implement RSB
...
somehow missed this earlier
2016-08-05 02:13:26 +01:00
Tillmann Karras
eb2e6e8bea
Implement some multiplies
2016-08-05 02:09:54 +01:00
Tillmann Karras
72c503016c
Fix Pack2x32To1x64
...
Not sure how to fix this properly.
2016-08-05 02:09:30 +01:00
Tillmann Karras
3fdc093d10
Add more IR opcodes for multiply instructions
...
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
2016-08-05 02:09:30 +01:00
Tillmann Karras
af27ef8d6c
Optionally disassemble x86_64 code using LLVM
2016-08-05 02:08:41 +01:00
bunnei
691e4139fa
arm: Implement B/BL/BX instructions.
2016-08-03 16:49:01 -04:00
Tillmann Karras
fc33f1d374
Implement more instructions
...
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
2016-08-03 00:47:17 +01:00
Tillmann Karras
30a90295b9
Implement data processing instructions
...
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST
The code could use some serious deduplication...
2016-08-03 00:47:16 +01:00
Tillmann Karras
fe71cc9d78
Disassemble reg-shifted regs in lower case
2016-08-03 00:47:16 +01:00
Tillmann Karras
2488926341
Add IR opcode RotateRightExtended
...
to rotate through the carry flag
2016-08-03 00:47:16 +01:00
Tillmann Karras
306e070ab5
Use opcodes.inc for emit_x64.h
2016-08-03 00:44:08 +01:00
Tillmann Karras
61eddbd1fa
Fix Linux build
2016-08-03 00:44:08 +01:00
MerryMage
1252bd653d
RegAlloc: Define constructors for HostLocInfo to make MSVC happy
2016-08-03 00:25:42 +01:00
MerryMage
a875c0c720
TranslateArm: Stub more ARM instructions
2016-08-02 21:59:33 +01:00
MerryMage
deb5e2c10d
IR::DumpBlock: Incorrect use of std::map::at
2016-08-02 13:47:05 +01:00
MerryMage
4414ec5bc8
RegAlloc: Allow allocation of XMM registers
2016-08-02 13:46:12 +01:00
MerryMage
864081d1a0
BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR
2016-08-02 12:00:11 +01:00
MerryMage
6097a21955
TranslateArm: Reorganisation - Split visitor into multiple .cpp files
2016-08-02 11:54:04 +01:00
MerryMage
93af160c97
arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface
2016-08-02 11:54:02 +01:00
MerryMage
be87038ffd
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
MerryMage
51448aa06d
More Speed
2016-07-22 23:55:00 +01:00
MerryMage
5fbfc6c155
Implement some simple IR optimizations (get/set eliminiation and DCE)
2016-07-21 21:48:45 +01:00
MerryMage
90d317b868
Implement memory endianness. Implement Thumb SETEND instruction.
2016-07-20 15:34:17 +01:00
MerryMage
98bd7ff6a5
Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support.
2016-07-20 12:08:17 +01:00
Merry
95316b8443
Merged in Subv/dynarmic/arm_mem_tests (pull request #4 )
...
Added some fuzz tests for most cases of ARM Load/Store instructions
2016-07-20 10:19:55 +01:00
MerryMage
95588d3faa
Fix Thumb BLX (imm), BL (imm) for negative immediates
2016-07-18 22:48:23 +01:00
MerryMage
3f11a149d7
Implement Thumb Instructions: BLX (imm), BL (imm)
2016-07-18 22:18:58 +01:00
MerryMage
e0d6e28b67
Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2)
2016-07-18 21:04:39 +01:00
Subv
ccc61472b9
Added format strings for ARM STRBT encodings A1 and A2
2016-07-18 14:20:58 -05:00
Subv
8617bf80a1
Added format strings for ARM LDRBT encodings A1 and A2
2016-07-18 14:18:39 -05:00
Subv
5d5ea9325c
Added format strings for ARM STRT encodings A1 and A2
2016-07-18 14:05:53 -05:00
MerryMage
2363759c62
Implement thumb STM, LDM. Fix thumb POP implementation for P=1.
2016-07-18 20:05:35 +01:00
MerryMage
8a310777a1
backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC
2016-07-18 20:01:48 +01:00
Subv
77761ba032
Added the format strings for LDRT encodings A1 and A2.
2016-07-18 14:01:18 -05:00
MerryMage
14dcb18bbe
Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2)
2016-07-18 18:48:08 +01:00
MerryMage
a605a43ef9
Implement Thumb Instructions: STRH (imm), LDRH (imm)
2016-07-18 18:28:52 +01:00
MerryMage
f9755870bb
Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg)
2016-07-18 18:02:02 +01:00
Merry
3b8790bf29
Merged in Subv/dynarmic/small_opt (pull request #3 )
...
Pass the current IR::Block by reference to the emitter.
2016-07-18 17:38:12 +01:00
MerryMage
dfef65d98f
Implement thumb POP instruction
2016-07-18 17:37:48 +01:00
Subv
703a46ec99
Pass the current IR::Block by reference to the emitter.
...
This avoids calling the copy constructor more times than needed.
2016-07-18 11:27:33 -05:00
MerryMage
f7e3d7b8d2
Implement Thumb PUSH instruction
2016-07-18 15:11:16 +01:00
MerryMage
9109b226af
Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm)
2016-07-18 11:16:12 +01:00
MerryMage
c18a3eeab4
Better MSVC support
...
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
2016-07-18 10:38:22 +01:00
MerryMage
bf99ddd065
Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic
2016-07-18 10:33:52 +01:00
MerryMage
28a201da16
Implement Thumb ADR instruction
2016-07-18 09:25:33 +01:00
Subv
0cdf5fe751
Implemented ARM REV and REVSH instructions, with tests.
2016-07-17 14:45:42 -05:00
Merry
24aa24b1bc
Merged in Subv/dynarmic (pull request #1 )
...
Implemented ARM CMP (imm) instruction.
2016-07-17 19:43:49 +01:00
Subv
7f09510945
Implemented ARM CMP (imm) instruction.
2016-07-17 13:29:37 -05:00
MerryMage
3720da4e19
Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH}
2016-07-16 19:23:42 +01:00
MerryMage
4b1c27e64f
Implement arm_ADC_imm
2016-07-14 20:02:41 +01:00
MerryMage
63242924fc
Implement thumb16_SVC
2016-07-14 15:01:30 +01:00
MerryMage
181f78f36e
Common: Remove src/common/logging/log.*
2016-07-14 14:55:08 +01:00
MerryMage
07eaf100ba
Reorganise src/frontend: Add subdirectories disassembler and translate
2016-07-14 14:39:43 +01:00
MerryMage
9b2aff166a
Implement arm_SVC
2016-07-14 14:29:46 +01:00
MerryMage
672ffb93d0
frontend/translator: Skeleton for Arm translator
2016-07-14 13:28:20 +01:00
MerryMage
7d7751c157
Allow IR blocks to require a cond for block entry.
...
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
2016-07-14 12:52:53 +01:00
MerryMage
4ab4ca58f9
backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight
2016-07-14 09:02:27 +01:00
MerryMage
08e848044d
backend_x64: Inline Routines::GenReturnFromRunCode into emitted code
2016-07-12 16:46:27 +01:00
MerryMage
619b451902
clang support
2016-07-12 14:31:43 +01:00
MerryMage
8449deb0bc
MSVC support
2016-07-12 13:28:09 +01:00
MerryMage
44352680c6
s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones
2016-07-12 11:09:34 +01:00
MerryMage
6e46e7899a
Translate/Thumb: Fallback to interpreter for Thumb32 instructions
2016-07-12 11:02:45 +01:00
MerryMage
09420d190b
IR: Implement IR microinstructions ALUWritePC and LoadWritePC
2016-07-12 10:58:14 +01:00
MerryMage
f85b86486b
frontend/TranslateArm: Just interpret all ARM instructions
2016-07-12 09:11:35 +01:00
MerryMage
1410221b47
Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg
2016-07-11 23:11:05 +01:00
MerryMage
e7922e4fef
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +01:00
MerryMage
cbcf61a9e6
backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI
2016-07-11 15:28:10 +01:00
MerryMage
f0f14fa5e8
Implement thumb1_MOV_reg
2016-07-10 13:10:06 +08:00
MerryMage
8920ce79b9
Implement thumb_CMP_reg_t2
2016-07-10 12:23:16 +08:00
MerryMage
ac2fb6b925
Implement thumb1_MVN_reg
2016-07-10 10:49:01 +08:00
MerryMage
d11df9067d
Implement thumb1_BIC_reg
2016-07-10 10:44:45 +08:00
MerryMage
98a64a92b1
Implement thumb1_ORR_reg
2016-07-10 09:06:38 +08:00
MerryMage
3fe46d2c6f
Implement thumb1_CMN_reg
2016-07-10 08:55:56 +08:00
MerryMage
641dbf8eb4
Implement thumb1_CMP_reg
2016-07-10 08:52:28 +08:00
MerryMage
46408267c3
Implement thumb1_RSB_imm
2016-07-10 08:44:07 +08:00
MerryMage
6536ad9618
Implement thumb1_TST_reg
2016-07-10 08:35:58 +08:00
MerryMage
8145b33882
Implemented thumb1_ROR_reg
2016-07-10 08:18:17 +08:00
MerryMage
207cb74dc9
Implement thumb1_SBC_reg
2016-07-09 08:27:41 +08:00
MerryMage
1953e44532
Implement thumb1_ADC_reg
2016-07-08 22:17:39 +08:00
MerryMage
9e9fa62d5f
Implement thumb1_SUB_imm_t2
2016-07-08 21:48:55 +08:00
MerryMage
8c587df8ce
Implement thumb1_ADD_imm_t2
2016-07-08 21:38:43 +08:00
MerryMage
aa72323823
Implement thumb1_CMP_imm
2016-07-08 21:32:01 +08:00
MerryMage
98f300144b
Implement thumb1_MOV_imm
2016-07-08 21:27:27 +08:00
MerryMage
34be20e4d6
Implement thumb1_SUB_imm
2016-07-08 20:57:53 +08:00
MerryMage
a2e40eb922
Implement thumb1_ADD_imm
2016-07-08 19:15:30 +08:00
MerryMage
92142d5a22
Implement thumb1_SUB_reg
2016-07-08 18:49:30 +08:00
MerryMage
df0c324923
Implement thumb1_EOR_reg
2016-07-08 18:14:54 +08:00
MerryMage
8a0511d297
Implement thumb1_AND_reg
2016-07-08 17:44:53 +08:00
MerryMage
5b56fd12aa
Fix bug: Correct disassembly of thumb1_LSL_reg, thumb1_LSR_reg, thumb1_ASR_reg
2016-07-08 17:44:52 +08:00
MerryMage
d0b48bfb59
Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2
2016-07-08 17:44:51 +08:00
MerryMage
e93fb0ba2b
EmitX64: remove emit_fns map, use a switch statement instead
2016-07-08 15:28:56 +08:00
MerryMage
421ab344ad
EmitX64::EmitTerminalInterpret: Restore RSP before CALL
2016-07-07 22:03:45 +08:00
MerryMage
e5f6450a24
Start implementing Thumb disassembler
2016-07-07 21:51:47 +08:00
MerryMage
f31b530703
Fuzz thumb instructions
2016-07-07 19:01:47 +08:00
MerryMage
5711e62419
Implement terminal instructions
2016-07-07 17:53:09 +08:00
MerryMage
14388ea690
Proper implementation of Arm::Translate
2016-07-04 21:37:50 +08:00
MerryMage
d743adf518
Reorganisation, Import Skyeye, This is a mess
2016-07-04 17:22:11 +08:00
MerryMage
be1c1de552
Common: Add scope_exit.h
2016-07-04 14:56:41 +08:00
MerryMage
6a37072865
Tidy up CMakeLists.txt
2016-07-01 21:23:39 +08:00
MerryMage
2be0639308
Removed daggen
2016-07-01 21:23:22 +08:00
MerryMage
65df15633d
First Commit
2016-07-01 21:01:06 +08:00
