Lioncash
e5d80e998e
A64: Implement SADDLV
2020-04-22 20:46:21 +01:00
Lioncash
a1bc8ddb53
A64: Implement UADDLV
2020-04-22 20:46:21 +01:00
Lioncash
af3e23b224
simd_scalar_shift_by_immediate: Implement FCVT{ZS, ZU} (vector, fixed-point)'s scalar double/single-precision variant
2020-04-22 20:46:21 +01:00
Lioncash
91abf87169
simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants
...
We can simply implement this in terms of the fixed-point IR opcodes.
2020-04-22 20:46:21 +01:00
MerryMage
a40127a054
A64: Implement FRINTX, FRINTI (scalar)
2020-04-22 20:46:20 +01:00
MerryMage
962fa3b65e
A64: Implement FRINTP, FRINTM, FRINTZ (scalar)
2020-04-22 20:46:20 +01:00
MerryMage
5200bf41cf
A64: Implement FRINTN (scalar)
2020-04-22 20:46:20 +01:00
MerryMage
8718dc1692
A64: Implement FRINTA (scalar)
2020-04-22 20:46:20 +01:00
Lioncash
f7f83b76b7
simd_scalar_two_register_misc: Implement scalar double/single-precision variants of FCM{EQ, GE, GT, LE, LT} (zero)
2020-04-22 20:46:20 +01:00
MerryMage
89e43867c1
A64: Implement FADDP (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
33fa65de23
A64: Implement FADDP (vector)
2020-04-22 20:46:19 +01:00
MerryMage
9dba273a8c
A64: Implement SADDLP
2020-04-22 20:46:19 +01:00
MerryMage
70ff2d73b5
A64: Implement UADDLP
2020-04-22 20:46:19 +01:00
MerryMage
5563bbbd79
A64: Implement EXT
2020-04-22 20:46:19 +01:00
MerryMage
3d9677d094
A64: Implement FCVTMU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
79c9018d60
A64: Implement FCVTMS (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
49c4499a87
A64: Implement FCVTPU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
af661ef5a6
A64: Implement FCVTPS (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
27319822bb
A64: Implement FCVTAU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
c0c7a26314
A64: Implement FCVTAS (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
a1965a74a0
A64: Implement FCVTNU (scalar)
2020-04-22 20:46:19 +01:00
MerryMage
7d36dbcdfd
A64: Implement FCVTNS (scalar)
2020-04-22 20:46:19 +01:00
Lioncash
e7409fdfe4
A64: Implement UCVTF (vector, integer)'s double/single-precision variant
2020-04-22 20:46:19 +01:00
Lioncash
a1d6a86e8c
A64: Implement ADDV
2020-04-22 20:46:19 +01:00
Lioncash
9912836b59
A64: Implement scalar double/single-precision variants of FACGE, FACGT, FCMEQ, FCMGE, FCMGT
2020-04-22 20:46:18 +01:00
Lioncash
53dbb6a92a
A64: Implement FACGE's vector single/double precision variants
2020-04-22 20:46:18 +01:00
Lioncash
6912a02d9b
A64: Implement FACGT's vector single/double precision variants
2020-04-22 20:46:18 +01:00
Lioncash
593eca7fb1
A64: Implement load/store single structure instructions
...
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
2020-04-22 20:46:18 +01:00
Lioncash
9e75d08860
A64: Implement FABD's scalar single/double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
d898d1779d
A64: Implement FABD's vector single/double precision variant
2020-04-22 20:46:18 +01:00
MerryMage
ba84e7a8de
A64: Implement FNMSUB
2020-04-22 20:46:18 +01:00
MerryMage
a1042cfcd8
A64: Implement FNMADD
2020-04-22 20:46:18 +01:00
MerryMage
0d83032a6f
A64: Implement FMSUB
2020-04-22 20:46:18 +01:00
MerryMage
69e00d225c
A64: Implement FMADD
2020-04-22 20:46:18 +01:00
Lioncash
24e3299276
A64: Implement FCMGT, FCMGE (register) vector double and single precision variants
2020-04-22 20:46:18 +01:00
Lioncash
350bc70be8
A64: Implement FCMGT, FCMGE, FCMLE, FCMLT (zero) vector double and single precision variants.
2020-04-22 20:46:18 +01:00
Lioncash
d86fea0d28
A64: Implement FCMEQ (zero)'s vector single and double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
9bec354791
A64: Implement FCMEQ (register)'s vector single and double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
11a92eaaef
A64: Implement SRHADD and URHADD
2020-04-22 20:46:18 +01:00
Lioncash
cb456f914b
A64: Implement UMLAL{2}, UMLSL{2}, and UMULL{2}
...
Now that we have the helper function set up for the signed variants, we
can also modify it to be used with the unigned ones by performing a zero
extension instead of a sign extension.
2020-04-22 20:46:18 +01:00
Lioncash
3576c02d91
A64: Implement SMLSL{2}
2020-04-22 20:46:18 +01:00
Lioncash
ada5c0b2fa
A64: Implement SMLAL{2}
2020-04-22 20:46:18 +01:00
Lioncash
2d1aca25e6
A64: Implement SMULL{2}
2020-04-22 20:46:18 +01:00
Lioncash
c5ae9107a9
A64: Implement SABAL/SABAL2 and SABDL/SABDL2
...
Now that we have a helper function for the unsigned variants, we can
modify it to also be usable with the signed variants.
2020-04-22 20:46:18 +01:00
Lioncash
26d4473851
A64: Implement UABAL/UABAL2
2020-04-22 20:46:18 +01:00
Lioncash
3397742c74
A64: Implement UABDL/UABDL2
2020-04-22 20:46:18 +01:00
Lioncash
9054d1c20b
A64: Implement LDR (literal, SIMD&FP)
2020-04-22 20:46:18 +01:00
Lioncash
9736e2cce2
A64: Implement FABS' half-precision variant
2020-04-22 20:46:18 +01:00
Lioncash
6e5750e4ec
A64: Implement FABS' single and double precision variant
2020-04-22 20:46:18 +01:00
Lioncash
7bce8d8757
A64: Implement URSHR (scalar) and URSRA (scalar)
...
Now that the utility function is all set up from implementing SRSRA, the
unsigned variants can now be trivially implemented by modifying the
utility function to perform a logical shift right instead of an
arithmetical shift right for the unsigned case.
2020-04-22 20:46:18 +01:00
