MerryMage
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cc9efd13c9
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A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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81713c2b77
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ef906dbbfa
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A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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44c3c2312a
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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2ee39d6b36
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A64: Implement FMOV (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b02b861242
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A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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5a65313236
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A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ab4664de61
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A64: Implement CCMN (immediate)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
a6c6539109
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A64: Implement CCMP (register)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
22632db337
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microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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c5033b5dda
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A64: Implement CCMN (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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dd2a6684fe
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IR: Add ConditionalSelectNZCV instruction
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
12c6f841c2
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inst_gen: Make invalid_instructions a static inline variable
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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f96e83c486
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fuzz_with_unicorn: Move instruction generator vector into GenRandomInst
Keeps scope localized and prevents potential static initialization issues.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4491746eae
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A64: Implement FNEG
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
db958061a3
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A64: Implement FABS
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
8765b421b7
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A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
7e82d8eede
|
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
2409e5d082
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b173fcf34e
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backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
56bc7825ef
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A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
d040920727
|
Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
40614202e7
|
A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ccef85dbb7
|
A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
68f46c8334
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backend_x64: Use a reference to BlockOfCode instead of a pointer
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
8931ee346b
|
IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
0bb4474fb9
|
A64: Implement INS (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
d13704fdef
|
A64: Implement INS (element)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
0642d49919
|
A64: Implement SMOV
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
5297027ebe
|
A64: Implement UMOV
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
47661b746b
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
1fb0957aa3
|
A64: Implement FCVT
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ca38225e08
|
fuzz_with_unicorn: Skip instructions that need to be interpreted
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
4be55b8b84
|
A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
a07c05ea51
|
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
93fcbdf1e2
|
A64: Implement FCMP, FCMPE
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
75b8a76630
|
a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
429dc24587
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IR: Merge U32 and U64 variants of FP instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ed2bedec43
|
A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
6414736a8d
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emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ebfc51c609
|
IR: Implement VectorSetElement{8,16,32,64}
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
744495e23d
|
iterator_util: Make Reverse constexpr
C++17 makes non-member rbegin(), rend(), crbegin(), and crend() constexpr, allowing this to also be constexpr.
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
ab9b5fb8aa
|
Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
af1384d700
|
A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
01b4395bf8
|
travis: Bump MACOSX_DEPLOYMENT_TARGET
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
7e0f14303c
|
fuzz_with_unicorn: Print information on test failure
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
64761dbc72
|
scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
|
2020-04-22 20:46:12 +01:00 |
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