MerryMage
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bcde135c23
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emit_x64_crc32: Improve 64-bit PCLMULQDQ implementation of EmitCRC32ISO
Reduce number of PCLMULQDQs to 3
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2020-06-04 19:23:51 +01:00 |
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MerryMage
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0f9c70ff42
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emit_x64_crc32: Improve PCLMULQDQ implementation of EmitCRC32ISO
Remove use of pshufd
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2020-06-03 18:55:58 +01:00 |
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MerryMage
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fa6aee434e
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emit_x64_crc32: PCLMULQDQ implementation of EmitCRC32ISO
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2020-06-03 11:16:53 +01:00 |
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MerryMage
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b47adaee1d
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emit_x64_vector: SSSE3 implementation of EmitVectorExtract
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2020-06-01 15:41:36 +01:00 |
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MerryMage
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f3845cea9a
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A32: Implement ASIMD VQSUB instruction
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2020-05-30 18:19:17 +01:00 |
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MerryMage
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16ff880f8f
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A32: Implement ASIMD VQADD
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2020-05-30 16:09:37 +01:00 |
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MerryMage
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174fbb74c5
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simd_three_same: Use VectorSaturated{Signed,Unsigned}{Add,Sub} in SaturatingArithmeticOperation
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2020-05-30 15:55:32 +01:00 |
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MerryMage
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4e90754873
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IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub}
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2020-05-30 15:55:32 +01:00 |
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MerryMage
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3a50d444dc
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A32: Implement ASIMD VHSUB
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2020-05-28 22:29:00 +01:00 |
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MerryMage
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205e6c5a56
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A32: Implement ASIMD VRHADD
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2020-05-28 22:29:00 +01:00 |
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MerryMage
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946eb03a3b
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A32: Implement ASIMD VHADD
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2020-05-28 22:29:00 +01:00 |
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MerryMage
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f8062345bb
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asimd_two_regs_misc: Use {Get,Set}Vector
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2020-05-28 21:05:30 +01:00 |
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MerryMage
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11cec1e3b6
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asimd_three_same: Use {Get,Set}Vector
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2020-05-28 21:05:16 +01:00 |
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MerryMage
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7d0b16de32
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asimd_one_reg_modified_immediate: Use {Get,Set}Vector
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2020-05-28 20:40:26 +01:00 |
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MerryMage
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cae857b8c8
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verification_pass: Have an appropriate assertion message
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2020-05-28 20:40:11 +01:00 |
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MerryMage
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ebddf6cca0
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basic_block: Allow printing of invalid instruction pointers
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2020-05-28 20:39:50 +01:00 |
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MerryMage
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07108246cf
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A32/IR: Add SetVector and GetVector
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2020-05-28 20:39:19 +01:00 |
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MerryMage
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e85a08ec34
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CMakeLists: MSVC: Weaken warning level for externals
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2020-05-26 20:52:06 +01:00 |
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MerryMage
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93c289b54f
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Use tsl::robin_map and tsl::robin_set
Replace std::unordered_map and std::unordered_set with the above.
Better performance profile.
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2020-05-26 20:51:48 +01:00 |
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MerryMage
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91578edc69
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externals: Add robin-map
Merge commit '8bf66a678af746fce336851a8ddf8fa08d358a20' as 'externals/robin-map'
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2020-05-26 20:51:29 +01:00 |
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MerryMage
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8bf66a678a
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Squashed 'externals/robin-map/' content from commit 5cf53c6f5
git-subtree-dir: externals/robin-map
git-subtree-split: 5cf53c6f5d81ba31a475f66ac4a61c6f54e476d3
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2020-05-26 20:51:11 +01:00 |
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Lioncash
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c4a4bdd7de
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frontend: Relocate ExtReg handling to types.h
Same behavior, but deduplicates the code being placed across several
files
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2020-05-24 23:55:47 +01:00 |
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Lioncash
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1900df5340
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frontend: Relocate advanced SIMD expansion to a common file
Deduplicates code a little bit.
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2020-05-24 23:55:47 +01:00 |
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Lioncash
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fc112e61f2
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A32: Implement ASIMD modified immediate functions
Implements VBIC, VMOV, VMVN, and VORR modified immediate instructions.
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2020-05-24 23:55:47 +01:00 |
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Lioncash
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659d78c9c4
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A32: Implement ASIMD VSWP
A trivial one to implement, this just swaps the contents of two
registers in place.
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2020-05-22 19:43:24 +01:00 |
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MerryMage
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d0d50c4824
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print_info: Use VFP and ASIMD decoders to get dynarmic name for instruction
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2020-05-17 22:48:14 +01:00 |
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MerryMage
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d0075f4ea6
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print_info: Use LLVM to disassemble A32
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2020-05-17 22:30:46 +01:00 |
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MerryMage
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c59a127e86
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opcodes: Switch from std::map to std::array
Optimization.
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2020-05-17 17:01:39 +01:00 |
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MerryMage
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d0b45f6150
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A32: Implement ARMv8 VST{1-4} (multiple)
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2020-05-17 17:01:39 +01:00 |
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Lioncash
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eb332b3836
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asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction
Now that all bitwise instructions are implemented, we can unify all of
them together using if constexpr.
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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f42b3ad4a0
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A32: Implement ASIMD VBIF (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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ee9a81dcba
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A32: Implement ASIMD VBIT (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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d624059ead
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A32: Implement ASIMD VBSL (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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66663cf8e7
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asimd_three_same: Collapse all bitwise implementations into a single code path
Less code and results in only writing the parts that matter once.
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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4b5e3437cf
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A32: Implement ASIMD VEOR (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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67b284f6fa
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A32: Implement ASIMD VORN (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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1fdd90ca2a
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A32: Implement ASIMD VORR (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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9b93a9de46
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a32_jitstate: Remove obsoleted debug assert
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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64fa804dd4
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A32: Implement ASIMD VBIC (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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0441ab81a1
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A32: Implement ASIMD VAND (register)
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2020-05-16 20:22:12 +01:00 |
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Lioncash
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1b25e867ae
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asimd_load_store_structures: Simplify ToExtRegD()
ExtReg has a supplied operator+, so we can make use of that instead.
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2020-05-16 11:27:22 -04:00 |
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MerryMage
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2169653c50
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a64_emit_x64: Invalid regalloc code for EmitA64ExclusiveReadMemory128
Attempted to allocate args[0] after end of allocation scope
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2020-05-16 14:11:23 +01:00 |
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MerryMage
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1a0bc5ba91
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A32/ASIMD: ARMv8: Implement VLD{1-4} (multiple)
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2020-05-16 14:11:23 +01:00 |
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MerryMage
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e7f1a0d408
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A32: ARMv8: Implement LDA{,EX}{,B,D,H} and STL{,EX}{,B,D,H}
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2020-05-15 21:07:36 +01:00 |
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Lioncash
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8808b8c479
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cpu_info: Make test non-allocating
Same behavior, but makes it non-allocating by using a constexpr
std::array instead of a std::vector.
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2020-05-12 09:52:55 +01:00 |
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Lioncash
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af3b65b135
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decoder_detail: Mark GetMaskAndExpect() as constexpr
Elides quite a bit of code at runtime when constructing the decoding
tables.
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2020-05-11 08:29:06 +01:00 |
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MerryMage
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59db2c191a
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VFPv3: Implement VMOV (immediate)
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2020-05-10 15:09:37 +01:00 |
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MerryMage
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7f77a04900
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fuzz_arm: Do not test vfp_VMRS
This may emit a vmrs *, fpscr instruction.
This results in fuzz failures due to slight inaccuracies in fpscr emulation.
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2020-05-10 14:47:21 +01:00 |
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MerryMage
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3c86d58064
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VFPv4: Implement VCVTB, VCVTT
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2020-05-10 14:45:18 +01:00 |
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MerryMage
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010fab9a0e
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VFPv4: Implement VFMA, VFMS
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2020-05-10 14:20:11 +01:00 |
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