MerryMage
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98c8e7d1af
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IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eae518a338
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IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b9cd345ddc
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IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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851fc83445
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emit_x64_vector: EmitOneArgumentFallback
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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303088a51e
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IR: Implement VectorPopulationCount
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bf2cd92da9
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emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b062266b8e
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emit_x64_vector: More explicit lambda decay
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b6de612e01
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IR: Implement VectorMultiply
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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90a053a5e4
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emit_x64_vector: Order alphabetically
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1423584f9f
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constant_pool: Allow for 128-bit constants
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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69de50a878
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
f6247125c0
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
d74f4e35f6
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block_of_code: Increase constant pool size
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
e69288f803
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devirtualize: MinGW uses Intanium MFP ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ad428cbd7a
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callback: Properly handle calls with return pointers and simplify interface
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
7a87e3fc55
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devirtualize: Handle Windows ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
f808a0fbde
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devirtualize: Devirtualize Itanium ABI MFPs at runtime
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
35a29a9665
|
A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
|
FernandoS27
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586854117b
|
Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
44c3c2312a
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
dd2a6684fe
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IR: Add ConditionalSelectNZCV instruction
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
b173fcf34e
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backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
d040920727
|
Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
|
2020-04-22 20:46:13 +01:00 |
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Lioncash
|
40614202e7
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
ccef85dbb7
|
A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
68f46c8334
|
backend_x64: Use a reference to BlockOfCode instead of a pointer
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
8931ee346b
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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75b8a76630
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a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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6414736a8d
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emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1
This bug wasn't discovered earlier because we previously only used index == 0.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ebfc51c609
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IR: Implement VectorSetElement{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab9b5fb8aa
|
Common: Relocate common bits of CRC32
Allows the algorithm to be used in any other potential backend.
|
2020-04-22 20:46:12 +01:00 |
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Lioncash
|
af1384d700
|
A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
64761dbc72
|
scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT
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2020-04-22 20:46:12 +01:00 |
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MerryMage
|
bafb39ebc5
|
A64: Add Disassemble method
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2020-04-22 20:46:12 +01:00 |
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MerryMage
|
f023bbb893
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A32: Add ExceptionRaised IR instruction and use it
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2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
d7044bc751
|
assert: Use fmt in ASSERT_MSG
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
52268298a8
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a64_emit_x64: Perform RSB predictions
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
98ec9c5f90
|
A32: Change UserCallbacks to be similar to A64's interface
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
b9ce660113
|
reg_alloc: std::move RegAlloc's function argument
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
ed561d6653
|
General: Add missing override specifiers
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
b2d99eddc6
|
EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128
|
2020-04-22 20:46:12 +01:00 |
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