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72 commits

Author SHA1 Message Date
Lioncash
e4c259d69f frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes 2020-04-22 20:58:12 +01:00
Lioncash
bd892ec4ef frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point 2020-04-22 20:58:11 +01:00
Lioncash
597a8be5d5 ir: Add A64-specific opcodes for getting and setting raw NZCV values 
This will be necessary to implement the flag manipulation and flag
format instructions.
 2020-04-22 20:58:11 +01:00
Lioncash
5cf1478620 frontend/ir: Add opcodes for vector square roots 2020-04-22 20:58:10 +01:00
Lioncash
36027ebef5 frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
This was intended to be added within #437, but was missed
 2020-04-22 20:58:10 +01:00
Lioncash
d426dfe942 ir: Add opcodes for unsigned saturating left shifts 2020-04-22 20:55:06 +01:00
MerryMage
02150bc0b7 IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed 2020-04-22 20:55:06 +01:00
MerryMage
90193b0e3d IR: Add fbits argument to FixedToFP-related opcodes 2020-04-22 20:55:06 +01:00
Lioncash
b14eaaec46 ir: Add opcodes for left signed saturated shifts 2020-04-22 20:55:06 +01:00
MerryMage
3e447614c6 IR: Add VectorSignedSaturatedDoublingMultiplyLong 2020-04-22 20:55:06 +01:00
MerryMage
06b31448aa emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply 
* Return both the upper and lower parts of the multiply if required
* SSE2 does not support the pmuldq instruction, do sign correction to an unsigned result instead
* Improve port utilisation where possible (punpck instructions were a bottleneck)
 2020-04-22 20:55:06 +01:00
MerryMage
08c0e017a5 IR: Implement Vector{Signed,Unsigned}Multiply{16,32} 2020-04-22 20:55:06 +01:00
Lioncash
d4a76aaa04 ir: Add opcodes form unsigned saturated accumulations of signed values 2020-04-22 20:55:05 +01:00
Lioncash
6f911a26da ir: Add opcodes for signed saturated accumulations of unsigned values 2020-04-22 20:55:05 +01:00
Lioncash
fca7eddb9e A64: Add opcodes for signed saturating negations 2020-04-22 20:53:46 +01:00
Lioncash
a0231e5546 ir: Add opcodes for signed saturated doubling multiplies 2020-04-22 20:53:46 +01:00
Lioncash
0507e47420 ir: Add opcodes for signed saturated absolute values 2020-04-22 20:53:46 +01:00
MerryMage
ccbf6c7f63 microinstruction: A32ExceptionRaised causes CPU exception 2020-04-22 20:53:46 +01:00
MerryMage
89d08c7d61 IR: Add VectorTable and VectorTableLookup IR instructions 2020-04-22 20:53:45 +01:00
Lioncash
f3f60cd179 A64: Implement ISB 
Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
 2020-04-22 20:53:45 +01:00
MerryMage
3f4d118d73 microinstruction: Improve assert messages 2020-04-22 20:46:23 +01:00
MerryMage
ddcff86f9c microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits 2020-04-22 20:46:22 +01:00
MerryMage
ecbf9dbae5 IR: Implement A64OrQC 2020-04-22 20:46:22 +01:00
MerryMage
b455b566e7 A64: Implement UQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
3874cb37e3 A64: Implement SQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage
f020dbe4ed A64: Implement SQXTUN 2020-04-22 20:46:22 +01:00
MerryMage
6918ef7360 microinstruction: Reorganize FPSCR related instruction queries 2020-04-22 20:46:22 +01:00
Lioncash
a639fa5534 microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() 
These were forgotten when the opcodes were added.
 2020-04-22 20:46:22 +01:00
Subv
4606a081c9 A64: The A64SetTPIDR IR instruction writes to a system register and should not be eliminated by the dead code elimination pass. 
Previously this instruction was alway eliminated, resulting in incorrect values for TPIDR_EL0.
 2020-04-22 20:46:21 +01:00
MerryMage
e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage
b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2020-04-22 20:46:14 +01:00
MerryMage
bfd65bedfe A64: Implement DSB, DMB 2020-04-22 20:46:14 +01:00
MerryMage
5edd623b9d Implement DC instructions 2020-04-22 20:46:14 +01:00
MerryMage
f378d2ef1b Forward declare IR::Opcode and IR::Type where possible 2020-04-22 20:46:14 +01:00
Lioncash
22632db337 microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement 2020-04-22 20:46:13 +01:00
MerryMage
6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass 2020-04-22 20:46:12 +01:00
MerryMage
b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
Lioncash
67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage
94383fd934 microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2020-04-22 20:44:38 +01:00
MerryMage
394bd57bb6 microinstruction: bug: Add missing opcodes 2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage
0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage
25411da838 A32: Implement load stores (immediate) 2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05 A64: Implement SVC 2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5 A64: PSTATE access and tests 2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3 A64: Implement branch (register) 2020-04-22 20:42:45 +01:00
MerryMage
0641445e51 A64: Implement logical 2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97 A64: Implement addsub instructions 2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00