Lioncash
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40614202e7
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ccef85dbb7
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A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
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8931ee346b
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0bb4474fb9
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A64: Implement INS (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
d13704fdef
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A64: Implement INS (element)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
0642d49919
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A64: Implement SMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
5297027ebe
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A64: Implement UMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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47661b746b
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basic_block: Fix bogus GCC maybe-uninitialized warning
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
1fb0957aa3
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A64: Implement FCVT
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ca38225e08
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fuzz_with_unicorn: Skip instructions that need to be interpreted
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
4be55b8b84
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A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
a07c05ea51
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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
93fcbdf1e2
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A64: Implement FCMP, FCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
429dc24587
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IR: Merge U32 and U64 variants of FP instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ed2bedec43
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ebfc51c609
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IR: Implement VectorSetElement{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
af1384d700
|
A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
cc0eb18a0b
|
A32: data_processing: Remove !S assertions
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
865a30eb0d
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A32: Implement BKPT
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
f023bbb893
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A32: Add ExceptionRaised IR instruction and use it
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2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
d7044bc751
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assert: Use fmt in ASSERT_MSG
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2020-04-22 20:46:12 +01:00 |
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MerryMage
|
52268298a8
|
a64_emit_x64: Perform RSB predictions
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
98ec9c5f90
|
A32: Change UserCallbacks to be similar to A64's interface
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
6fc228f7fd
|
ir_opt: Add A64 Get/Set Elimination Pass
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2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
e01b500aea
|
ir_emitter: Allow the insertion point for new instructions to be set
|
2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
7734cf1050
|
A64: Implement EXTR
|
2020-04-22 20:46:12 +01:00 |
|
MerryMage
|
88ae7fce52
|
A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
b513b2ef05
|
IR: Implement IR instructions A64{Get,Set}S
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2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
|
2020-04-22 20:44:38 +01:00 |
|
Lioncash
|
7abd673a49
|
A64: Zero upper 64 bits in ORN if using the 64-bit variant
Resolves a TODO
|
2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
ba3d6da0c8
|
load_store_register_unprivileged: bug: LDTRSW
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
75756137c6
|
A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
d5283e46e8
|
IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
|
e0c12ec2ad
|
A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
|
MerryMage
|
94383fd934
|
microinstruction: Missed A64{Read,Write}Memory128 from opcode information
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
589ad7232f
|
Fixup: Xn|SP are 64 bit addresses encoded in the Rn field
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
ae880d8391
|
A64: Fix bugs and address review comments
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
3aeb7ca50c
|
Add missing returns
|
2020-04-22 20:44:38 +01:00 |
|
James Rowe
|
41e6e659c5
|
A64: Implement Load/Store register (unprivileged)
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
285fd22c30
|
IR: Add IR instruction VectorZeroUpper
|
2020-04-22 20:44:37 +01:00 |
|
FernandoS27
|
ab84524806
|
Implemented SDIV and UDIV instructions
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
6033b05ca6
|
A64: Implement LDR/STR (immediate, SIMD&FP)
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
e1df7ae621
|
IR: Add IR instructions A64Memory{Read,Write}128
This implementation only works on macOS and Linux.
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
e00a522cba
|
IR: Add IR instruction VectorGetElement{8,16,32,64}
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
28ccd85e5c
|
IR: Add IR instruction ZeroExtendToQuad
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
3caf192f60
|
A64: Implement DUP (general)
|
2020-04-22 20:44:37 +01:00 |
|
MerryMage
|
793753bf63
|
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
|
2020-04-22 20:44:37 +01:00 |
|