MerryMage
d1eb757f93
A64: Backend framework
2020-04-22 20:42:44 +01:00
MerryMage
e161cf16f5
A64: Initial framework
2020-04-22 20:42:44 +01:00
MerryMage
f61da0b5a9
IR: Compile-time type-checking of IR
2020-04-22 20:39:27 +01:00
MerryMage
44f7f04b5c
IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg
2020-04-22 20:39:27 +01:00
MerryMage
83022322d1
Make IR->A32 LocationDescriptor conversion explicit
2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1
Final A32 refactor
2020-04-22 20:39:27 +01:00
MerryMage
8bef20c24d
IR: Split off A32 specific opcodes
2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278
A32: Split off A32 specific IREmitter
2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622
Label A32 specific code appropriately
2020-04-22 20:33:30 +01:00
MerryMage
4393473d06
interface: Allow saving and storing of contexts
2020-04-22 20:26:40 +01:00
MerryMage
19a7fb8992
jit_state: Split off CPSR.NZCV
2020-04-22 20:26:40 +01:00
MerryMage
311361b409
jit_state: Split off CPSR.{E,T}
...
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72
emit_x64: Use boost::icl::interval_map to speed up ranged invalidation
2020-04-22 20:26:40 +01:00
MerryMage
80c56aa89d
Remove unnecessary use of boost::make_optional
...
Closes #119 .
2020-04-22 20:26:12 +01:00
MerryMage
de6a93a160
decoder_detail: Lambda captures may be unused if iota is an empty sequence
...
Closes #120
2020-04-22 20:26:12 +01:00
MerryMage
3141dadea9
Remove UNUSED macro
2020-04-22 20:26:12 +01:00
MerryMage
7cac9519b0
microinstruction: Remove DecrementRemainingUses
2020-04-22 20:26:12 +01:00
MerryMage
5d72f7048f
basic_block: Add inst address and use count to DumpBlock
...
This additional output assists with debugging.
2020-04-22 20:26:12 +01:00
MerryMage
d1e0a29cd9
Implement IR instruction PackedSelect, reimplement SEL
2020-04-22 20:26:07 +01:00
MerryMage
814e378249
VCMP and VCMPE were the other way around
...
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
2020-04-22 20:26:07 +01:00
MerryMage
29471be317
Standardize location of storage-class specifiers: Place at beginning of declarations
...
Justification: C99 specifies that doing otherwise is an obsolescent feature.
2017-09-29 01:23:45 +01:00
MerryMage
993e142c6b
disassembler: Fix RegList
2017-08-05 01:57:29 +01:00
MerryMage
6197bde0fc
disassembler_arm: Fix disassembly of LDRH (reg)
2017-07-30 18:45:55 +01:00
MerryMage
599a613fea
Move SEL from status_register_access to misc
2017-04-25 13:57:27 +01:00
MerryMage
50bb317104
parallel: UQADD8 and UQADD16 are unpredictable when {d|n|m} == 15
2017-04-25 13:45:31 +01:00
MerryMage
7639dfea51
coprocessor: Use && instead of & with boolean arguments
2017-04-22 15:05:31 +01:00
MerryMage
1c21ae6bcd
saturated: Implement QASX, QSAX, UQASX, UQSAX
2017-04-10 10:21:51 +01:00
MerryMage
523ae542f4
microinstruction: Implement HasAssociatedPseudoOperation
2017-04-04 13:10:50 +01:00
MerryMage
05e97058c3
parallel: Add and Subtract with Exchange improvements
...
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8
Ranged cache invalidation
2017-03-20 11:58:25 +00:00
MerryMage
92a01b0cd8
Prefer ASSERT to DEBUG_ASSERT
2017-02-26 23:30:40 +00:00
MerryMage
bbeea72eba
ir_opt: Remove redundant shift instructions
2017-02-26 15:28:14 +00:00
MerryMage
4ed8ee7489
microinstruction: Void arguments when invalidating instruction
2017-02-18 21:29:23 +00:00
MerryMage
7fa5845c1f
extension: Implement SXTAB16 and SXTB16
2017-02-18 20:14:44 +00:00
MerryMage
73d1cf36c3
extension: Simplify UXTB16
2017-02-18 20:14:39 +00:00
MerryMage
6edcfeba0b
extension: Simplify rotation code
2017-02-18 20:14:37 +00:00
MerryMage
cc9d2c4603
saturated: Implement SSAT16 and USAT16
2017-02-18 17:43:57 +00:00
MerryMage
358cf7c322
vfp: Implement vectorized VFP instructions
2017-02-18 01:13:25 +00:00
MerryMage
f2dd82967f
load_store: Simplify implementation
...
* Remove dead code
* Standardise code style with rest of code base
2017-02-16 22:28:56 +00:00
MerryMage
5a20a37d3f
arm/fpscr: Correct Stride implementation
2017-02-11 12:13:57 +00:00
MerryMage
033e8b9b1e
vfp: Rename variables a, b, c to more sensible names
2017-02-06 21:14:36 +00:00
MerryMage
642ccb0f66
ir/value: Support U16 immediates
2017-01-29 22:58:11 +00:00
MerryMage
5f7ffe0d0b
microinstruction: Implement Inst::AreAllArgsImmediates
2017-01-29 22:56:59 +00:00
MerryMage
22804dc6a5
microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const
2017-01-29 22:53:46 +00:00
MerryMage
1d4446cad5
microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith
2017-01-29 22:52:33 +00:00
MerryMage
e3bc7d039f
Implement CDP, LDC, MCR, MCRR, MRC, MRRC, STC
2017-01-08 14:56:06 +00:00
MerryMage
48693eb6ff
Implement coprocessor-related microinstructions
...
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
2017-01-08 14:56:06 +00:00
MerryMage
b3ae57619d
types: Formatting for CoprogReg
2017-01-08 14:56:06 +00:00
MerryMage
d8a37e287c
IR: Add IR type CoprocInfo
2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d
IR: Remove unused microinstructions NegateLowWord and NegateHighWord
2017-01-05 20:16:39 +00:00
