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966 commits

Author SHA1 Message Date
Merry
01bb1cdd88 Merge pull request #458 from lioncash/float-op 
A64: Handle half-precision floating point in FABS, FNEG, and scalar FMOV
 2020-04-22 20:58:12 +01:00
Lioncash
28a8b4d210 A64: Handle half-precision floating point in scalar FMOV 
This is simply performing a scalar value transfer between registers
without conversions, so this is trivial to handle as-is.
 2020-04-22 20:58:12 +01:00
Lioncash
d7ac5a664f A64: Handle half-precision floating point in FCVTL 
Like FCVTN, now that we have half-precision floating point conversion
functions available, we can go ahead and use those to eliminate the
interpreter fallback.
 2020-04-22 20:58:12 +01:00
Lioncash
fe84ecb780 A64: Handle half-precision floating point in scalar FABS 
Now that we have the half-precision variant of the opcode added, we can
simply handle the instruction instead of treating it as undefined.
 2020-04-22 20:58:12 +01:00
Lioncash
fac9224d5e A64: Handle half-precision floating point in FCVTN 
Now that we have IR instructions for performing conversions with
half-precision floating point, we can also handle half-precision values
within FCVTN.
 2020-04-22 20:58:12 +01:00
Lioncash
8309ec7a9f frontend/ir_emitter: Add half-precision variant of FPAbs 2020-04-22 20:58:12 +01:00
Lioncash
16de99d3e3 A64: Enable FCVT floating-point conversions for half-precision 
With this, we no longer have to fall back to the interpreter in any of
the FCVT floating-point conversion instructions.
 2020-04-22 20:58:12 +01:00
Lioncash
10abc77fad A64: Handle half-precision floating point in scalar FNEG 
With the half-precision variant of the FPNeg opcode added, we can
utilize it here to emulate the half-precision variant of FNEG.
 2020-04-22 20:58:12 +01:00
Lioncash
e4c259d69f frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes 2020-04-22 20:58:12 +01:00
Lioncash
c97efcb978 frontend/ir_emitter: Add half-precision variant of FPNeg 2020-04-22 20:58:12 +01:00
Merry
f01afc5ae6 Merge pull request #456 from lioncash/mov 
A64: Enable FMOV (general) for half-precision floating point
 2020-04-22 20:58:12 +01:00
Merry
c1ce94872d Merge pull request #455 from lioncash/sqrdmulh-scalar 
A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
 2020-04-22 20:58:11 +01:00
Lioncash
25a7256ee1 A64: Enable FMOV (general) for half-precision floating point 
This just transfers values between vector registers and general-purpose
registers with no conversions performed, so this is trivial to add
support for half-precision to.
 2020-04-22 20:58:11 +01:00
Lioncash
97dd3d0596 A64: Implement SQRDMULH's scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
49b51e34f1 simd_vector_x_indexed_element: Deduplicate index and Vm operand construction 2020-04-22 20:58:11 +01:00
Lioncash
692aba91b6 A64: Implement SQDMULL{2}'s scalar indexed element variant 2020-04-22 20:58:11 +01:00
Lioncash
c043b831d5 A64: Implement SQDMULL{2}'s by-element variant 2020-04-22 20:58:11 +01:00
Lioncash
72af5a3dff simd_scalar_x_indexed_element: Factor out index and Vm argument construction 
This will be useful in the implementations of SQRDMULH and SQDMULL{2} as
well.
 2020-04-22 20:58:11 +01:00
Lioncash
224ff0afaa A64: Implement SQRDMULH's by-index vector variant 2020-04-22 20:58:11 +01:00
Lioncash
3a3542414b A64: Implement FRECPX's half-precision floating point variant 2020-04-22 20:58:11 +01:00
Lioncash
bd892ec4ef frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point 2020-04-22 20:58:11 +01:00
Lioncash
974fbf0677 frontend/ir/value: Add U16U32U64 type to represent floating point types 2020-04-22 20:58:11 +01:00
Lioncash
126c29a9e9 A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants 
These can just be implemented in terms of the vector variants for the
time being.
 2020-04-22 20:58:11 +01:00
Lioncash
dd7433f9d3 A64: Amend prototypes of some SIMD scalar shift by immediate opcodes 
These take a vector for a destination.
 2020-04-22 20:58:11 +01:00
Merry
bbd5330ad2 Merge pull request #447 from lioncash/flag 
A64: Implement CFINV, RMIF, AXFlag and XAFlag
 2020-04-22 20:58:11 +01:00
Merry
fb039e232c Merge pull request #442 from lioncash/fcvtxn 
A64: Implement scalar and vector variants of FCVTXN
 2020-04-22 20:58:11 +01:00
Merry
4f937c1ee1 Merge pull request #446 from lioncash/sqshl 
A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
 2020-04-22 20:58:11 +01:00
Lioncash
aa22db534b A64: Implement AXFlag and XAFlag 2020-04-22 20:58:11 +01:00
Merry
d74cccbc84 Merge pull request #445 from lioncash/sqrt 
A64: Implement single and double-precision vector variant of FSQRT
 2020-04-22 20:58:11 +01:00
Lioncash
20ffe568d0 A64: Implement RMIF 2020-04-22 20:58:11 +01:00
Merry
6d7e7c3269 Merge pull request #443 from lioncash/flag 
A64: Rearrange flag format/manipulation instructions
 2020-04-22 20:58:11 +01:00
Lioncash
51b526e453 A64: Implement CFINV 2020-04-22 20:58:11 +01:00
Lioncash
597a8be5d5 ir: Add A64-specific opcodes for getting and setting raw NZCV values 
This will be necessary to implement the flag manipulation and flag
format instructions.
 2020-04-22 20:58:11 +01:00
Lioncash
d3515279df A64: Implement the vector version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
17aea0b997 A64: Implement UQSHL (register)'s scalar variant 
This can be implemented in terms of the vector variant.
 2020-04-22 20:58:10 +01:00
Lioncash
c99d4b762e A64: Implement single and double-precision vector variant of FSQRT 2020-04-22 20:58:10 +01:00
Lioncash
54e0b487f3 A64: Rearrange flag format/manipulation instructions 
Gives these instructions better categorical labeling.
 2020-04-22 20:58:10 +01:00
Lioncash
302f56b36a A64: Fall back to interpreting for FCADD and FCMLA half-precision variants 
Rather than straight-up treating them as undefined, we can fall back to an
interpreter in this case.
 2020-04-22 20:58:10 +01:00
Lioncash
4339a8fff6 A64: Implement the scalar version of FCVTXN 2020-04-22 20:58:10 +01:00
Lioncash
35ddf68ad5 A64: Implement SQSHL (register)'s scalar variant 
We can implement this in terms of the vector variant.
 2020-04-22 20:58:10 +01:00
Lioncash
5cf1478620 frontend/ir: Add opcodes for vector square roots 2020-04-22 20:58:10 +01:00
Lioncash
36027ebef5 frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
This was intended to be added within #437, but was missed
 2020-04-22 20:58:10 +01:00
Lioncash
7c81a58ed3 frontend/ir/ir_emitter: Alter parameters of FPDoubleToSingle() and FPSingleToDouble() to pass along desired rounding mode 
This will be necessary to special-case the non-IEEE Von Neumann rounding
to odd rounding mode.
 2020-04-22 20:58:10 +01:00
Merry
40b081438a Merge pull request #439 from lioncash/fcmla 
A64: Implement FCADD and FCMLA
 2020-04-22 20:58:10 +01:00
Merry
d91192681a Merge pull request #438 from lioncash/fmulx 
A64: Implement scalar double/single precision FMULX (by element)
 2020-04-22 20:58:10 +01:00
Lioncash
ed29ef8cca A64: Implement FCMLA 2020-04-22 20:58:10 +01:00
Merry
9f11720a69 Merge pull request #437 from lioncash/frecpx 
A64: Implement FRECPX (single, double precision)
 2020-04-22 20:58:10 +01:00
Lioncash
bdcea0b0dc A64: Implement scalar double/single precision FMULX (by element) 2020-04-22 20:58:10 +01:00
Lioncash
5ce17574f9 A64: Implement FCADD 2020-04-22 20:58:10 +01:00
Merry
34d917f34e Merge pull request #436 from lioncash/no-alloc 
A64: Implement LDNP/STNP
 2020-04-22 20:58:10 +01:00