FernandoS27
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586854117b
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Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1a7b7b541a
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A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate)
There wasn't a clean way to seperate these instructions out.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8ab7d8175c
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impl: Add AdvSIMDExpandImm
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ea69cb4474
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A64: Implement SUB (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4c5871d5d5
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A64: Implement ADD (vector), scalar variant
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
2a0850c068
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A64: Reorganize decoder tables (some vector entries were grouped with scalar entries)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
7b33772ac6
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A64: Implement BIC (vector, register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ca43be4146
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docs: Update documentation (2018-02-05)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
eb5591859c
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A64: Implement FMOV (general)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
dd88cee15a
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translate/impl: Add Vpart
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
cc9efd13c9
|
A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
81713c2b77
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A64: Implement FCCMPE
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ef906dbbfa
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A64: Implement FCCMP
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
44c3c2312a
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
2ee39d6b36
|
A64: Implement FMOV (register)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b02b861242
|
A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
5a65313236
|
A64: Implement CCMP (immediate)
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ab4664de61
|
A64: Implement CCMN (immediate)
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
a6c6539109
|
A64: Implement CCMP (register)
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
22632db337
|
microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
c5033b5dda
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A64: Implement CCMN (register)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
dd2a6684fe
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IR: Add ConditionalSelectNZCV instruction
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
12c6f841c2
|
inst_gen: Make invalid_instructions a static inline variable
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
f96e83c486
|
fuzz_with_unicorn: Move instruction generator vector into GenRandomInst
Keeps scope localized and prevents potential static initialization issues.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4491746eae
|
A64: Implement FNEG
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
db958061a3
|
A64: Implement FABS
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8765b421b7
|
A64: Implement FCSEL
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
7e82d8eede
|
A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
2409e5d082
|
A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
b173fcf34e
|
backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
|
2020-04-22 20:46:13 +01:00 |
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MerryMage
|
56bc7825ef
|
A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register)
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
d040920727
|
Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
40614202e7
|
A64: Implement AESD
|
2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ccef85dbb7
|
A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
68f46c8334
|
backend_x64: Use a reference to BlockOfCode instead of a pointer
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
8931ee346b
|
IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
0bb4474fb9
|
A64: Implement INS (general)
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
d13704fdef
|
A64: Implement INS (element)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
0642d49919
|
A64: Implement SMOV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
5297027ebe
|
A64: Implement UMOV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
47661b746b
|
basic_block: Fix bogus GCC maybe-uninitialized warning
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
1fb0957aa3
|
A64: Implement FCVT
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
ca38225e08
|
fuzz_with_unicorn: Skip instructions that need to be interpreted
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
4be55b8b84
|
A64: Implement FMOV (scalar, immediate)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
a07c05ea51
|
A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
93fcbdf1e2
|
A64: Implement FCMP, FCMPE
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
75b8a76630
|
a64_jitstate: A64 does not have a seperate FPSCR.NZCV
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
99d8ebe4d5
|
A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
|
2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
429dc24587
|
IR: Merge U32 and U64 variants of FP instructions
|
2020-04-22 20:46:13 +01:00 |
|