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dynarmic/src/frontend/ir/opcodes.inc

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ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
// opcode name, return type, arg1 type, arg2 type, arg3 type, ...
First Commit
2016-07-01 14:01:06 +01:00
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(Void, T::Void, )
OPCODE(Identity, T::Opaque, T::Opaque )
OPCODE(Breakpoint, T::Void, )
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
// A32 Context getters/setters
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
A32OPC(GetRegister, T::U32, T::A32Reg )
A32OPC(GetExtendedRegister32, T::U32, T::A32ExtReg )
A32OPC(GetExtendedRegister64, T::U64, T::A32ExtReg )
A32OPC(SetRegister, T::Void, T::A32Reg, T::U32 )
A32OPC(SetExtendedRegister32, T::Void, T::A32ExtReg, T::U32 )
A32OPC(SetExtendedRegister64, T::Void, T::A32ExtReg, T::U64 )
A32OPC(GetCpsr, T::U32, )
A32OPC(SetCpsr, T::Void, T::U32 )
A32OPC(SetCpsrNZCV, T::Void, T::U32 )
A32OPC(SetCpsrNZCVQ, T::Void, T::U32 )
A32OPC(GetNFlag, T::U1, )
A32OPC(SetNFlag, T::Void, T::U1 )
A32OPC(GetZFlag, T::U1, )
A32OPC(SetZFlag, T::Void, T::U1 )
A32OPC(GetCFlag, T::U1, )
A32OPC(SetCFlag, T::Void, T::U1 )
A32OPC(GetVFlag, T::U1, )
A32OPC(SetVFlag, T::Void, T::U1 )
A32OPC(OrQFlag, T::Void, T::U1 )
A32OPC(GetGEFlags, T::U32, )
A32OPC(SetGEFlags, T::Void, T::U32 )
A32OPC(SetGEFlagsCompressed, T::Void, T::U32 )
A32OPC(BXWritePC, T::Void, T::U32 )
A32OPC(CallSupervisor, T::Void, T::U32 )
A32OPC(ExceptionRaised, T::Void, T::U32, T::U64 )
A32OPC(GetFpscr, T::U32, )
A32OPC(SetFpscr, T::Void, T::U32, )
A32OPC(GetFpscrNZCV, T::U32, )
A32OPC(SetFpscrNZCV, T::Void, T::NZCVFlags )
First Commit
2016-07-01 14:01:06 +01:00
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
// A64 Context getters/setters
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
A64OPC(SetCheckBit, T::Void, T::U1 )
A64OPC(GetCFlag, T::U1, )
A64OPC(SetNZCV, T::Void, T::NZCVFlags )
A64OPC(GetW, T::U32, T::A64Reg )
A64OPC(GetX, T::U64, T::A64Reg )
//A64OPC(GetB, T::U128, T::A64Vec )
//A64OPC(GetH, T::U128, T::A64Vec )
A64OPC(GetS, T::U128, T::A64Vec )
A64OPC(GetD, T::U128, T::A64Vec )
A64OPC(GetQ, T::U128, T::A64Vec )
A64OPC(GetSP, T::U64, )
A64OPC(GetFPCR, T::U32, )
A64OPC(GetFPSR, T::U32, )
A64OPC(SetW, T::Void, T::A64Reg, T::U32 )
A64OPC(SetX, T::Void, T::A64Reg, T::U64 )
//A64OPC(SetB, T::Void, T::A64Vec, T::U8 )
//A64OPC(SetH, T::Void, T::A64Vec, T::U16 )
A64OPC(SetS, T::Void, T::A64Vec, T::U128 )
A64OPC(SetD, T::Void, T::A64Vec, T::U128 )
A64OPC(SetQ, T::Void, T::A64Vec, T::U128 )
A64OPC(SetSP, T::Void, T::U64 )
A64OPC(SetFPCR, T::Void, T::U32 )
A64OPC(SetFPSR, T::Void, T::U32 )
A64OPC(SetPC, T::Void, T::U64 )
A64OPC(CallSupervisor, T::Void, T::U32 )
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )
A64OPC(DataCacheOperationRaised, T::Void, T::U64, T::U64 )
A64OPC(DataSynchronizationBarrier, T::Void, )
A64OPC(DataMemoryBarrier, T::Void, )
A64OPC(GetCNTPCT, T::U64, )
A64OPC(GetCTR, T::U32, )
A64OPC(GetDCZID, T::U32, )
A64OPC(GetTPIDR, T::U64, )
A64OPC(SetTPIDR, T::Void, T::U64 )
A64OPC(GetTPIDRRO, T::U64, )
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
// Hints
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(PushRSB, T::Void, T::U64 )
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
// Pseudo-operation, handled special ly at final emit
OPCODE(GetCarryFromOp, T::U1, T::U32 )
OPCODE(GetOverflowFromOp, T::U1, T::U32 )
OPCODE(GetGEFromOp, T::U32, T::U32 )
OPCODE(GetNZCVFromOp, T::NZCVFlags, T::Opaque )
First Commit
2016-07-01 14:01:06 +01:00
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(NZCVFromPackedFlags, T::NZCVFlags, T::U32 )
IR: Add IR instruction NZCVFromPackedFlags This instruction expects NZCV to be in the high bits. i.e.: The positions they were in PSTATE.
2018-02-03 13:34:40 +00:00
First Commit
2016-07-01 14:01:06 +01:00
// Calculations
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(Pack2x32To1x64, T::U64, T::U32, T::U32 )
OPCODE(Pack2x64To1x128, T::U128, T::U64, T::U64 )
OPCODE(LeastSignificantWord, T::U32, T::U64 )
OPCODE(MostSignificantWord, T::U32, T::U64 )
OPCODE(LeastSignificantHalf, T::U16, T::U32 )
OPCODE(LeastSignificantByte, T::U8, T::U32 )
OPCODE(MostSignificantBit, T::U1, T::U32 )
OPCODE(IsZero32, T::U1, T::U32 )
OPCODE(IsZero64, T::U1, T::U64 )
OPCODE(TestBit, T::U1, T::U64, T::U8 )
OPCODE(ConditionalSelect32, T::U32, T::Cond, T::U32, T::U32 )
OPCODE(ConditionalSelect64, T::U64, T::Cond, T::U64, T::U64 )
OPCODE(ConditionalSelectNZCV, T::NZCVFlags, T::Cond, T::NZCVFlags, T::NZCVFlags )
OPCODE(LogicalShiftLeft32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftLeft64, T::U64, T::U64, T::U8 )
OPCODE(LogicalShiftRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftRight64, T::U64, T::U64, T::U8 )
OPCODE(ArithmeticShiftRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(ArithmeticShiftRight64, T::U64, T::U64, T::U8 )
OPCODE(RotateRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(RotateRight64, T::U64, T::U64, T::U8 )
OPCODE(RotateRightExtended, T::U32, T::U32, T::U1 )
OPCODE(Add32, T::U32, T::U32, T::U32, T::U1 )
OPCODE(Add64, T::U64, T::U64, T::U64, T::U1 )
OPCODE(Sub32, T::U32, T::U32, T::U32, T::U1 )
OPCODE(Sub64, T::U64, T::U64, T::U64, T::U1 )
OPCODE(Mul32, T::U32, T::U32, T::U32 )
OPCODE(Mul64, T::U64, T::U64, T::U64 )
OPCODE(SignedMultiplyHigh64, T::U64, T::U64, T::U64 )
OPCODE(UnsignedMultiplyHigh64, T::U64, T::U64, T::U64 )
OPCODE(UnsignedDiv32, T::U32, T::U32, T::U32 )
OPCODE(UnsignedDiv64, T::U64, T::U64, T::U64 )
OPCODE(SignedDiv32, T::U32, T::U32, T::U32 )
OPCODE(SignedDiv64, T::U64, T::U64, T::U64 )
OPCODE(And32, T::U32, T::U32, T::U32 )
OPCODE(And64, T::U64, T::U64, T::U64 )
OPCODE(Eor32, T::U32, T::U32, T::U32 )
OPCODE(Eor64, T::U64, T::U64, T::U64 )
OPCODE(Or32, T::U32, T::U32, T::U32 )
OPCODE(Or64, T::U64, T::U64, T::U64 )
OPCODE(Not32, T::U32, T::U32 )
OPCODE(Not64, T::U64, T::U64 )
OPCODE(SignExtendByteToWord, T::U32, T::U8 )
OPCODE(SignExtendHalfToWord, T::U32, T::U16 )
OPCODE(SignExtendByteToLong, T::U64, T::U8 )
OPCODE(SignExtendHalfToLong, T::U64, T::U16 )
OPCODE(SignExtendWordToLong, T::U64, T::U32 )
OPCODE(ZeroExtendByteToWord, T::U32, T::U8 )
OPCODE(ZeroExtendHalfToWord, T::U32, T::U16 )
OPCODE(ZeroExtendByteToLong, T::U64, T::U8 )
OPCODE(ZeroExtendHalfToLong, T::U64, T::U16 )
OPCODE(ZeroExtendWordToLong, T::U64, T::U32 )
OPCODE(ZeroExtendLongToQuad, T::U128, T::U64 )
OPCODE(ByteReverseWord, T::U32, T::U32 )
OPCODE(ByteReverseHalf, T::U16, T::U16 )
OPCODE(ByteReverseDual, T::U64, T::U64 )
OPCODE(CountLeadingZeros32, T::U32, T::U32 )
OPCODE(CountLeadingZeros64, T::U64, T::U64 )
OPCODE(ExtractRegister32, T::U32, T::U32, T::U32, T::U8 )
OPCODE(ExtractRegister64, T::U64, T::U64, T::U64, T::U8 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
// Saturated instructions
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )
OPCODE(SignedSaturatedSub, T::U32, T::U32, T::U32 )
OPCODE(UnsignedSaturation, T::U32, T::U32, T::U8 )
OPCODE(SignedSaturation, T::U32, T::U32, T::U8 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
// Packed instructions
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(PackedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSubU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubU8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedAbsDiffSumS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSelect, T::U32, T::U32, T::U32, T::U32 )
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +01:00
A64: Implement CRC32C
2018-01-25 17:51:45 +00:00
// CRC instructions
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(CRC32Castagnoli8, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli16, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli32, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli64, T::U32, T::U32, T::U64 )
OPCODE(CRC32ISO8, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO16, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO32, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO64, T::U32, T::U32, T::U64 )
A64: Implement CRC32C
2018-01-25 17:51:45 +00:00
A64: Implement AESIMC and AESMC
2018-01-30 12:56:18 +00:00
// AES instructions
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(AESDecryptSingleRound, T::U128, T::U128 )
OPCODE(AESEncryptSingleRound, T::U128, T::U128 )
OPCODE(AESInverseMixColumns, T::U128, T::U128 )
OPCODE(AESMixColumns, T::U128, T::U128 )
ir: Add an opcode for doing an SM4 lookup table query
2018-05-07 13:29:12 +01:00
// SM4 instructions
OPCODE(SM4AccessSubstitutionBox, T::U8, T::U8 )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
// Vector instructions
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorGetElement8, T::U8, T::U128, T::U8 )
OPCODE(VectorGetElement16, T::U16, T::U128, T::U8 )
OPCODE(VectorGetElement32, T::U32, T::U128, T::U8 )
OPCODE(VectorGetElement64, T::U64, T::U128, T::U8 )
OPCODE(VectorSetElement8, T::U128, T::U128, T::U8, T::U8 )
OPCODE(VectorSetElement16, T::U128, T::U128, T::U8, T::U16 )
OPCODE(VectorSetElement32, T::U128, T::U128, T::U8, T::U32 )
OPCODE(VectorSetElement64, T::U128, T::U128, T::U8, T::U64 )
ir: Add opcodes for performing vector absolute values
2018-04-02 21:27:04 +01:00
OPCODE(VectorAbs8, T::U128, T::U128 )
OPCODE(VectorAbs16, T::U128, T::U128 )
OPCODE(VectorAbs32, T::U128, T::U128 )
OPCODE(VectorAbs64, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorAdd8, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd64, T::U128, T::U128, T::U128 )
OPCODE(VectorAnd, T::U128, T::U128, T::U128 )
OPCODE(VectorArithmeticShiftRight8, T::U128, T::U128, T::U8 )
OPCODE(VectorArithmeticShiftRight16, T::U128, T::U128, T::U8 )
OPCODE(VectorArithmeticShiftRight32, T::U128, T::U128, T::U8 )
OPCODE(VectorArithmeticShiftRight64, T::U128, T::U128, T::U8 )
OPCODE(VectorBroadcastLower8, T::U128, T::U8 )
OPCODE(VectorBroadcastLower16, T::U128, T::U16 )
OPCODE(VectorBroadcastLower32, T::U128, T::U32 )
OPCODE(VectorBroadcast8, T::U128, T::U8 )
OPCODE(VectorBroadcast16, T::U128, T::U16 )
OPCODE(VectorBroadcast32, T::U128, T::U32 )
OPCODE(VectorBroadcast64, T::U128, T::U64 )
ir: Add opcodes for performing vector deinterleaving
2018-04-24 16:58:01 +01:00
OPCODE(VectorDeinterleaveEven8, T::U128, T::U128, T::U128 )
OPCODE(VectorDeinterleaveEven16, T::U128, T::U128, T::U128 )
OPCODE(VectorDeinterleaveEven32, T::U128, T::U128, T::U128 )
OPCODE(VectorDeinterleaveEven64, T::U128, T::U128, T::U128 )
OPCODE(VectorDeinterleaveOdd8, T::U128, T::U128, T::U128 )
OPCODE(VectorDeinterleaveOdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorDeinterleaveOdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorDeinterleaveOdd64, T::U128, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorEor, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual8, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual16, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual32, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual64, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual128, T::U128, T::U128, T::U128 )
IR: Implement VectorExtract, VectorExtractLower IR instructions
2018-04-02 21:52:46 +01:00
OPCODE(VectorExtract, T::U128, T::U128, T::U128, T::U8 )
OPCODE(VectorExtractLower, T::U128, T::U128, T::U128, T::U8 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorGreaterS8, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS16, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS32, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS64, T::U128, T::U128, T::U128 )
ir: Add opcodes for performing halving adds
2018-05-04 13:22:14 +01:00
OPCODE(VectorHalvingAddS8, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingAddS16, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingAddS32, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingAddU8, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingAddU16, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingAddU32, T::U128, T::U128, T::U128 )
ir: Add opcodes for performing vector halving subtracts
2018-05-07 17:07:56 +01:00
OPCODE(VectorHalvingSubS8, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingSubS16, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingSubS32, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingSubU8, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingSubU16, T::U128, T::U128, T::U128 )
OPCODE(VectorHalvingSubU32, T::U128, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorInterleaveLower8, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower16, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower32, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower64, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveUpper8, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveUpper16, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveUpper32, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveUpper64, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalShiftLeft8, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftLeft16, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftLeft32, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftLeft64, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight8, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight16, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight32, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight64, T::U128, T::U128, T::U8 )
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants Also adds IR opcodes to dispatch said variants
2018-04-30 15:01:57 +01:00
OPCODE(VectorLogicalVShiftS8, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShiftS16, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShiftS32, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShiftS64, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShiftU8, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShiftU16, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShiftU32, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShiftU64, T::U128, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorMaxS8, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxS16, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxS32, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxS64, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU8, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU16, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU32, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU64, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS8, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS16, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS32, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS64, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU8, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU16, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU32, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU64, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply8, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply16, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply32, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply64, T::U128, T::U128, T::U128 )
OPCODE(VectorNarrow16, T::U128, T::U128 )
OPCODE(VectorNarrow32, T::U128, T::U128 )
OPCODE(VectorNarrow64, T::U128, T::U128 )
OPCODE(VectorNot, T::U128, T::U128 )
OPCODE(VectorOr, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower8, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower16, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower32, T::U128, T::U128, T::U128 )
A64: Implement SADDLP
2018-07-15 18:48:11 +01:00
OPCODE(VectorPairedAddSignedWiden8, T::U128, T::U128 )
OPCODE(VectorPairedAddSignedWiden16, T::U128, T::U128 )
OPCODE(VectorPairedAddSignedWiden32, T::U128, T::U128 )
A64: Implement UADDLP
2018-07-15 18:26:54 +01:00
OPCODE(VectorPairedAddUnsignedWiden8, T::U128, T::U128 )
OPCODE(VectorPairedAddUnsignedWiden16, T::U128, T::U128 )
OPCODE(VectorPairedAddUnsignedWiden32, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorPairedAdd8, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
OPCODE(VectorPopulationCount, T::U128, T::U128 )
ir: Add opcode for reversing bits in a vector
2018-04-03 13:46:01 +01:00
OPCODE(VectorReverseBits, T::U128, T::U128 )
ir: Add opcodes for performing rounding halving adds
2018-05-23 21:52:31 +01:00
OPCODE(VectorRoundingHalvingAddS8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddS16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddS32, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddU8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddU16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddU32, T::U128, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorShuffleHighHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleLowHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleWords, T::U128, T::U128, T::U8 )
OPCODE(VectorSignExtend8, T::U128, T::U128 )
OPCODE(VectorSignExtend16, T::U128, T::U128 )
OPCODE(VectorSignExtend32, T::U128, T::U128 )
OPCODE(VectorSignExtend64, T::U128, T::U128 )
ir: Add opcodes for signed absolute differences
2018-05-08 20:39:37 +01:00
OPCODE(VectorSignedAbsoluteDifference8, T::U128, T::U128, T::U128 )
OPCODE(VectorSignedAbsoluteDifference16, T::U128, T::U128, T::U128 )
OPCODE(VectorSignedAbsoluteDifference32, T::U128, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(VectorSub8, T::U128, T::U128, T::U128 )
OPCODE(VectorSub16, T::U128, T::U128, T::U128 )
OPCODE(VectorSub32, T::U128, T::U128, T::U128 )
OPCODE(VectorSub64, T::U128, T::U128, T::U128 )
OPCODE(VectorUnsignedAbsoluteDifference8, T::U128, T::U128, T::U128 )
OPCODE(VectorUnsignedAbsoluteDifference16, T::U128, T::U128, T::U128 )
OPCODE(VectorUnsignedAbsoluteDifference32, T::U128, T::U128, T::U128 )
OPCODE(VectorZeroExtend8, T::U128, T::U128 )
OPCODE(VectorZeroExtend16, T::U128, T::U128 )
OPCODE(VectorZeroExtend32, T::U128, T::U128 )
OPCODE(VectorZeroExtend64, T::U128, T::U128 )
OPCODE(VectorZeroUpper, T::U128, T::U128 )
OPCODE(ZeroVector, T::U128, )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point operations
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPAbs32, T::U32, T::U32 )
OPCODE(FPAbs64, T::U64, T::U64 )
OPCODE(FPAdd32, T::U32, T::U32, T::U32 )
OPCODE(FPAdd64, T::U64, T::U64, T::U64 )
OPCODE(FPCompare32, T::NZCVFlags, T::U32, T::U32, T::U1 )
OPCODE(FPCompare64, T::NZCVFlags, T::U64, T::U64, T::U1 )
OPCODE(FPDiv32, T::U32, T::U32, T::U32 )
OPCODE(FPDiv64, T::U64, T::U64, T::U64 )
OPCODE(FPMax32, T::U32, T::U32, T::U32 )
OPCODE(FPMax64, T::U64, T::U64, T::U64 )
OPCODE(FPMaxNumeric32, T::U32, T::U32, T::U32 )
OPCODE(FPMaxNumeric64, T::U64, T::U64, T::U64 )
OPCODE(FPMin32, T::U32, T::U32, T::U32 )
OPCODE(FPMin64, T::U64, T::U64, T::U64 )
OPCODE(FPMinNumeric32, T::U32, T::U32, T::U32 )
OPCODE(FPMinNumeric64, T::U64, T::U64, T::U64 )
OPCODE(FPMul32, T::U32, T::U32, T::U32 )
OPCODE(FPMul64, T::U64, T::U64, T::U64 )
IR: Implement FPMulAdd
2018-06-06 20:03:12 +01:00
OPCODE(FPMulAdd32, T::U32, T::U32, T::U32, T::U32 )
OPCODE(FPMulAdd64, T::U64, T::U64, T::U64, T::U64 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPNeg32, T::U32, T::U32 )
OPCODE(FPNeg64, T::U64, T::U64 )
IR: Implement FPRoundInt
2018-07-16 13:49:15 +01:00
OPCODE(FPRoundInt32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(FPRoundInt64, T::U64, T::U64, T::U8, T::U1 )
IR: Implement FPRSqrtEstimate
2018-07-22 18:18:22 +01:00
OPCODE(FPRSqrtEstimate32, T::U32, T::U32 )
OPCODE(FPRSqrtEstimate64, T::U64, T::U64 )
IR: Implement FPRSqrtStepFused
2018-07-23 22:02:28 +01:00
OPCODE(FPRSqrtStepFused32, T::U32, T::U32, T::U32 )
OPCODE(FPRSqrtStepFused64, T::U64, T::U64, T::U64 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPSqrt32, T::U32, T::U32 )
OPCODE(FPSqrt64, T::U64, T::U64 )
OPCODE(FPSub32, T::U32, T::U32, T::U32 )
OPCODE(FPSub64, T::U64, T::U64, T::U64 )
VFP: Implement VADD.{F32,F64}
2016-08-06 17:21:29 +01:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point conversions
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPSingleToDouble, T::U64, T::U32 )
OPCODE(FPDoubleToSingle, T::U32, T::U64 )
IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64} This implementation just falls-back to the software floating point implementation.
2018-06-30 10:49:47 +01:00
OPCODE(FPDoubleToFixedS32, T::U32, T::U64, T::U8, T::U8 )
OPCODE(FPDoubleToFixedS64, T::U64, T::U64, T::U8, T::U8 )
OPCODE(FPDoubleToFixedU32, T::U32, T::U64, T::U8, T::U8 )
OPCODE(FPDoubleToFixedU64, T::U64, T::U64, T::U8, T::U8 )
OPCODE(FPSingleToFixedS32, T::U32, T::U32, T::U8, T::U8 )
OPCODE(FPSingleToFixedS64, T::U64, T::U32, T::U8, T::U8 )
OPCODE(FPSingleToFixedU32, T::U32, T::U32, T::U8, T::U8 )
OPCODE(FPSingleToFixedU64, T::U64, T::U32, T::U8, T::U8 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPU32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPS32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPU32ToDouble, T::U64, T::U32, T::U1 )
ir: Add opcodes for converting S64 and U64 to double-precision values
2018-07-09 22:14:00 +01:00
OPCODE(FPU64ToDouble, T::U64, T::U64, T::U1 )
ir: Add opcodes for converting S64 and U64 to single-precision floating-point values
2018-07-10 00:32:30 +01:00
OPCODE(FPU64ToSingle, T::U32, T::U64, T::U1 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 )
ir: Add opcodes for converting S64 and U64 to double-precision values
2018-07-09 22:14:00 +01:00
OPCODE(FPS64ToDouble, T::U64, T::U64, T::U1 )
ir: Add opcodes for converting S64 and U64 to single-precision floating-point values
2018-07-10 00:32:30 +01:00
OPCODE(FPS64ToSingle, T::U32, T::U64, T::U1 )
Implement VCVT
2016-08-23 22:04:46 +01:00
IR: Implement FPVectorSub
2018-02-11 12:17:53 +00:00
// Floating-point vector instructions
ir: Extend FPVectorAbs opcode to also handle 16-bit elements for FP16
2018-07-07 19:48:16 +01:00
OPCODE(FPVectorAbs16, T::U128, T::U128 )
ir: Add opcodes for performing vector absolute floating-point values This will be usable for implementing FACGE and FACGT
2018-07-07 02:55:42 +01:00
OPCODE(FPVectorAbs32, T::U128, T::U128 )
OPCODE(FPVectorAbs64, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPVectorAdd32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorAdd64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorDiv32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorDiv64, T::U128, T::U128, T::U128 )
ir: Add opcodes for floating-point vector equalities
2018-06-02 21:11:40 +01:00
OPCODE(FPVectorEqual32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorEqual64, T::U128, T::U128, T::U128 )
ir: Add opcode for floating-point GE and GT comparisons The rest of the comparisons can be implemented in terms of these two
2018-06-04 00:39:21 +01:00
OPCODE(FPVectorGreater32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorGreater64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorGreaterEqual32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorGreaterEqual64, T::U128, T::U128, T::U128 )
A64: Implement FMUL (vector)
2018-04-02 21:02:57 +01:00
OPCODE(FPVectorMul32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorMul64, T::U128, T::U128, T::U128 )
A64: Implement FADDP (vector)
2018-07-15 22:41:10 +01:00
OPCODE(FPVectorPairedAddLower32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAddLower64, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorPairedAdd64, T::U128, T::U128, T::U128 )
A64: Implement FRSQRTE (vector), single/double variant
2018-07-23 22:46:12 +01:00
OPCODE(FPVectorRSqrtEstimate32, T::U128, T::U128 )
OPCODE(FPVectorRSqrtEstimate64, T::U128, T::U128 )
A64: Implement FRSQRTS (vector), single/double variant
2018-07-23 22:58:52 +01:00
OPCODE(FPVectorRSqrtStepFused32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorRSqrtStepFused64, T::U128, T::U128, T::U128 )
IR: Add opcode for packed word->f32 conversions
2018-04-19 20:12:00 +01:00
OPCODE(FPVectorS32ToSingle, T::U128, T::U128 )
ir: Add opcode to perform the vector conversion S64->F64 Unfortunately x86 prior to AVX-512 doesn't really give us any convenient instruction to do the work for us
2018-05-08 16:18:13 +01:00
OPCODE(FPVectorS64ToDouble, T::U128, T::U128 )
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
OPCODE(FPVectorSub32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorSub64, T::U128, T::U128, T::U128 )
ir: Add opcodes for vector conversion of u32/u64 to floating-point
2018-07-12 14:02:27 +01:00
OPCODE(FPVectorU32ToSingle, T::U128, T::U128 )
OPCODE(FPVectorU64ToDouble, T::U128, T::U128 )
IR: Implement FPVectorSub
2018-02-11 12:17:53 +00:00
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
// A32 Memory access
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
A32OPC(ClearExclusive, T::Void, )
A32OPC(SetExclusive, T::Void, T::U32, T::U8 )
A32OPC(ReadMemory8, T::U8, T::U32 )
A32OPC(ReadMemory16, T::U16, T::U32 )
A32OPC(ReadMemory32, T::U32, T::U32 )
A32OPC(ReadMemory64, T::U64, T::U32 )
A32OPC(WriteMemory8, T::Void, T::U32, T::U8 )
A32OPC(WriteMemory16, T::Void, T::U32, T::U16 )
A32OPC(WriteMemory32, T::Void, T::U32, T::U32 )
A32OPC(WriteMemory64, T::Void, T::U32, T::U64 )
A32OPC(ExclusiveWriteMemory8, T::U32, T::U32, T::U8 )
A32OPC(ExclusiveWriteMemory16, T::U32, T::U32, T::U16 )
A32OPC(ExclusiveWriteMemory32, T::U32, T::U32, T::U32 )
A32OPC(ExclusiveWriteMemory64, T::U32, T::U32, T::U32, T::U32 )
Implement coprocessor-related microinstructions * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords
2016-12-31 11:17:47 +00:00
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
// A64 Memory access
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
A64OPC(ClearExclusive, T::Void, )
A64OPC(SetExclusive, T::Void, T::U64, T::U8 )
A64OPC(ReadMemory8, T::U8, T::U64 )
A64OPC(ReadMemory16, T::U16, T::U64 )
A64OPC(ReadMemory32, T::U32, T::U64 )
A64OPC(ReadMemory64, T::U64, T::U64 )
A64OPC(ReadMemory128, T::U128, T::U64 )
A64OPC(WriteMemory8, T::Void, T::U64, T::U8 )
A64OPC(WriteMemory16, T::Void, T::U64, T::U16 )
A64OPC(WriteMemory32, T::Void, T::U64, T::U32 )
A64OPC(WriteMemory64, T::Void, T::U64, T::U64 )
A64OPC(WriteMemory128, T::Void, T::U64, T::U128 )
A64OPC(ExclusiveWriteMemory8, T::U32, T::U64, T::U8 )
A64OPC(ExclusiveWriteMemory16, T::U32, T::U64, T::U16 )
A64OPC(ExclusiveWriteMemory32, T::U32, T::U64, T::U32 )
A64OPC(ExclusiveWriteMemory64, T::U32, T::U64, T::U64 )
A64OPC(ExclusiveWriteMemory128, T::U32, T::U64, T::U128 )
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
Implement coprocessor-related microinstructions * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords
2016-12-31 11:17:47 +00:00
// Coprocessor
ir: Add opcodes for performing vector unsigned absolute differences
2018-04-01 19:21:14 +01:00
A32OPC(CoprocInternalOperation, T::Void, T::CoprocInfo )
A32OPC(CoprocSendOneWord, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocSendTwoWords, T::Void, T::CoprocInfo, T::U32, T::U32 )
A32OPC(CoprocGetOneWord, T::U32, T::CoprocInfo )
A32OPC(CoprocGetTwoWords, T::U64, T::CoprocInfo )
A32OPC(CoprocLoadWords, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocStoreWords, T::Void, T::CoprocInfo, T::U32 )
Reference in a new issue Copy permalink