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dynarmic/src/frontend/ir/opcodes.inc

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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
// opcode name, return type, arg1 type, arg2 type, arg3 type, ...
First Commit
2016-07-01 14:01:06 +01:00
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(Void, T::Void, )
OPCODE(Identity, T::Opaque, T::Opaque )
OPCODE(Breakpoint, T::Void, )
IROpt: Port get/set elimination pass to current IR
2016-08-02 11:51:05 +01:00
IR: Split off A32 specific opcodes
2018-01-01 16:19:43 +00:00
// A32 Context getters/setters
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
A32OPC(GetRegister, T::U32, T::A32Reg )
A32OPC(GetExtendedRegister32, T::U32, T::A32ExtReg )
A32OPC(GetExtendedRegister64, T::U64, T::A32ExtReg )
A32OPC(SetRegister, T::Void, T::A32Reg, T::U32 )
A32OPC(SetExtendedRegister32, T::Void, T::A32ExtReg, T::U32 )
A32OPC(SetExtendedRegister64, T::Void, T::A32ExtReg, T::U64 )
A32OPC(GetCpsr, T::U32, )
A32OPC(SetCpsr, T::Void, T::U32 )
A32OPC(SetCpsrNZCV, T::Void, T::U32 )
A32OPC(SetCpsrNZCVQ, T::Void, T::U32 )
A32OPC(GetNFlag, T::U1, )
A32OPC(SetNFlag, T::Void, T::U1 )
A32OPC(GetZFlag, T::U1, )
A32OPC(SetZFlag, T::Void, T::U1 )
A32OPC(GetCFlag, T::U1, )
A32OPC(SetCFlag, T::Void, T::U1 )
A32OPC(GetVFlag, T::U1, )
A32OPC(SetVFlag, T::Void, T::U1 )
A32OPC(OrQFlag, T::Void, T::U1 )
A32OPC(GetGEFlags, T::U32, )
A32OPC(SetGEFlags, T::Void, T::U32 )
A32OPC(SetGEFlagsCompressed, T::Void, T::U32 )
A32OPC(BXWritePC, T::Void, T::U32 )
A32OPC(CallSupervisor, T::Void, T::U32 )
A32OPC(ExceptionRaised, T::Void, T::U32, T::U64 )
A32OPC(GetFpscr, T::U32, )
A32OPC(SetFpscr, T::Void, T::U32, )
A32OPC(GetFpscrNZCV, T::U32, )
A32OPC(SetFpscrNZCV, T::Void, T::NZCVFlags )
First Commit
2016-07-01 14:01:06 +01:00
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
// A64 Context getters/setters
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
A64OPC(SetCheckBit, T::Void, T::U1 )
A64OPC(GetCFlag, T::U1, )
A64OPC(SetNZCV, T::Void, T::NZCVFlags )
A64OPC(GetW, T::U32, T::A64Reg )
A64OPC(GetX, T::U64, T::A64Reg )
//A64OPC(GetB, T::U128, T::A64Vec )
//A64OPC(GetH, T::U128, T::A64Vec )
A64OPC(GetS, T::U128, T::A64Vec )
A64OPC(GetD, T::U128, T::A64Vec )
A64OPC(GetQ, T::U128, T::A64Vec )
A64OPC(GetSP, T::U64, )
A64: Implement system registers FPCR and FPSR
2018-02-20 17:38:29 +00:00
A64OPC(GetFPCR, T::U32, )
A64OPC(GetFPSR, T::U32, )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
A64OPC(SetW, T::Void, T::A64Reg, T::U32 )
A64OPC(SetX, T::Void, T::A64Reg, T::U64 )
//A64OPC(SetB, T::Void, T::A64Vec, T::U8 )
//A64OPC(SetH, T::Void, T::A64Vec, T::U16 )
A64OPC(SetS, T::Void, T::A64Vec, T::U128 )
A64OPC(SetD, T::Void, T::A64Vec, T::U128 )
A64OPC(SetQ, T::Void, T::A64Vec, T::U128 )
A64OPC(SetSP, T::Void, T::U64 )
A64: Implement system registers FPCR and FPSR
2018-02-20 17:38:29 +00:00
A64OPC(SetFPCR, T::Void, T::U32 )
A64OPC(SetFPSR, T::Void, T::U32 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
A64OPC(SetPC, T::Void, T::U64 )
A64OPC(CallSupervisor, T::Void, T::U32 )
A64OPC(ExceptionRaised, T::Void, T::U64, T::U64 )
Implement DC instructions
2018-02-11 22:53:46 +00:00
A64OPC(DataCacheOperationRaised, T::Void, T::U64, T::U64 )
A64: Implement DSB, DMB
2018-02-11 23:27:28 +00:00
A64OPC(DataSynchronizationBarrier, T::Void, )
A64OPC(DataMemoryBarrier, T::Void, )
A64: Implement system register CNTPCT_EL0
2018-02-20 16:54:10 +00:00
A64OPC(GetCNTPCT, T::U64, )
A64: Implement system register CTR_EL0
2018-02-20 16:44:13 +00:00
A64OPC(GetCTR, T::U32, )
A64: Partially implement MRS
2018-02-12 00:06:44 +00:00
A64OPC(GetDCZID, T::U32, )
A64: Implement system register TPIDR_EL0
2018-02-20 17:56:20 +00:00
A64OPC(GetTPIDR, T::U64, )
A64OPC(SetTPIDR, T::Void, T::U64 )
A64: Partially implement MRS
2018-02-12 00:06:44 +00:00
A64OPC(GetTPIDRRO, T::U64, )
A64: Implement ADD_shifted
2018-01-07 00:11:57 +00:00
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
// Hints
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(PushRSB, T::Void, T::U64 )
Optimization: Implement Return Stack Buffer
2016-08-13 00:10:23 +01:00
First Commit
2016-07-01 14:01:06 +01:00
// Pseudo-operation, handled specially at final emit
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(GetCarryFromOp, T::U1, T::U32 )
OPCODE(GetOverflowFromOp, T::U1, T::U32 )
OPCODE(GetGEFromOp, T::U32, T::U32 )
OPCODE(GetNZCVFromOp, T::NZCVFlags, T::Opaque )
First Commit
2016-07-01 14:01:06 +01:00
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(NZCVFromPackedFlags, T::NZCVFlags, T::U32 )
IR: Add IR instruction NZCVFromPackedFlags This instruction expects NZCV to be in the high bits. i.e.: The positions they were in PSTATE.
2018-02-03 13:34:40 +00:00
First Commit
2016-07-01 14:01:06 +01:00
// Calculations
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(Pack2x32To1x64, T::U64, T::U32, T::U32 )
A64: Implement STXP, STLXP, LDXP, LDAXP
2018-02-13 12:50:50 +00:00
OPCODE(Pack2x64To1x128, T::U128, T::U64, T::U64 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(LeastSignificantWord, T::U32, T::U64 )
OPCODE(MostSignificantWord, T::U32, T::U64 )
OPCODE(LeastSignificantHalf, T::U16, T::U32 )
OPCODE(LeastSignificantByte, T::U8, T::U32 )
OPCODE(MostSignificantBit, T::U1, T::U32 )
OPCODE(IsZero32, T::U1, T::U32 )
OPCODE(IsZero64, T::U1, T::U64 )
OPCODE(TestBit, T::U1, T::U64, T::U8 )
OPCODE(ConditionalSelect32, T::U32, T::Cond, T::U32, T::U32 )
OPCODE(ConditionalSelect64, T::U64, T::Cond, T::U64, T::U64 )
OPCODE(ConditionalSelectNZCV, T::NZCVFlags, T::Cond, T::NZCVFlags, T::NZCVFlags )
OPCODE(LogicalShiftLeft32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftLeft64, T::U64, T::U64, T::U8 )
OPCODE(LogicalShiftRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(LogicalShiftRight64, T::U64, T::U64, T::U8 )
OPCODE(ArithmeticShiftRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(ArithmeticShiftRight64, T::U64, T::U64, T::U8 )
OPCODE(RotateRight32, T::U32, T::U32, T::U8, T::U1 )
OPCODE(RotateRight64, T::U64, T::U64, T::U8 )
OPCODE(RotateRightExtended, T::U32, T::U32, T::U1 )
OPCODE(Add32, T::U32, T::U32, T::U32, T::U1 )
OPCODE(Add64, T::U64, T::U64, T::U64, T::U1 )
OPCODE(Sub32, T::U32, T::U32, T::U32, T::U1 )
OPCODE(Sub64, T::U64, T::U64, T::U64, T::U1 )
OPCODE(Mul32, T::U32, T::U32, T::U32 )
OPCODE(Mul64, T::U64, T::U64, T::U64 )
OPCODE(SignedMultiplyHigh64, T::U64, T::U64, T::U64 )
OPCODE(UnsignedMultiplyHigh64, T::U64, T::U64, T::U64 )
OPCODE(UnsignedDiv32, T::U32, T::U32, T::U32 )
OPCODE(UnsignedDiv64, T::U64, T::U64, T::U64 )
OPCODE(SignedDiv32, T::U32, T::U32, T::U32 )
OPCODE(SignedDiv64, T::U64, T::U64, T::U64 )
OPCODE(And32, T::U32, T::U32, T::U32 )
OPCODE(And64, T::U64, T::U64, T::U64 )
OPCODE(Eor32, T::U32, T::U32, T::U32 )
OPCODE(Eor64, T::U64, T::U64, T::U64 )
OPCODE(Or32, T::U32, T::U32, T::U32 )
OPCODE(Or64, T::U64, T::U64, T::U64 )
OPCODE(Not32, T::U32, T::U32 )
OPCODE(Not64, T::U64, T::U64 )
OPCODE(SignExtendByteToWord, T::U32, T::U8 )
OPCODE(SignExtendHalfToWord, T::U32, T::U16 )
OPCODE(SignExtendByteToLong, T::U64, T::U8 )
OPCODE(SignExtendHalfToLong, T::U64, T::U16 )
OPCODE(SignExtendWordToLong, T::U64, T::U32 )
OPCODE(ZeroExtendByteToWord, T::U32, T::U8 )
OPCODE(ZeroExtendHalfToWord, T::U32, T::U16 )
OPCODE(ZeroExtendByteToLong, T::U64, T::U8 )
OPCODE(ZeroExtendHalfToLong, T::U64, T::U16 )
OPCODE(ZeroExtendWordToLong, T::U64, T::U32 )
OPCODE(ZeroExtendLongToQuad, T::U128, T::U64 )
OPCODE(ByteReverseWord, T::U32, T::U32 )
OPCODE(ByteReverseHalf, T::U16, T::U16 )
OPCODE(ByteReverseDual, T::U64, T::U64 )
OPCODE(CountLeadingZeros32, T::U32, T::U32 )
OPCODE(CountLeadingZeros64, T::U64, T::U64 )
OPCODE(ExtractRegister32, T::U32, T::U32, T::U32, T::U8 )
OPCODE(ExtractRegister64, T::U64, T::U64, T::U64, T::U8 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
// Saturated instructions
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(SignedSaturatedAdd, T::U32, T::U32, T::U32 )
OPCODE(SignedSaturatedSub, T::U32, T::U32, T::U32 )
OPCODE(UnsignedSaturation, T::U32, T::U32, T::U8 )
OPCODE(SignedSaturation, T::U32, T::U32, T::U8 )
Implement QADD, QSUB, QDADD, QDSUB
2016-12-15 22:33:20 +00:00
// Packed instructions
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(PackedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSubU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSubAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubU8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingAddSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedHalvingSubAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedAddS16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubU16, T::U32, T::U32, T::U32 )
OPCODE(PackedSaturatedSubS16, T::U32, T::U32, T::U32 )
OPCODE(PackedAbsDiffSumS8, T::U32, T::U32, T::U32 )
OPCODE(PackedSelect, T::U32, T::U32, T::U32, T::U32 )
Implement thumb1_LDR_literal, thumb1_LDR_imm_t1
2016-07-11 22:43:53 +01:00
A64: Implement CRC32C
2018-01-25 17:51:45 +00:00
// CRC instructions
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(CRC32Castagnoli8, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli16, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli32, T::U32, T::U32, T::U32 )
OPCODE(CRC32Castagnoli64, T::U32, T::U32, T::U64 )
OPCODE(CRC32ISO8, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO16, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO32, T::U32, T::U32, T::U32 )
OPCODE(CRC32ISO64, T::U32, T::U32, T::U64 )
A64: Implement CRC32C
2018-01-25 17:51:45 +00:00
A64: Implement AESIMC and AESMC
2018-01-30 12:56:18 +00:00
// AES instructions
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(AESDecryptSingleRound, T::U128, T::U128 )
OPCODE(AESEncryptSingleRound, T::U128, T::U128 )
OPCODE(AESInverseMixColumns, T::U128, T::U128 )
OPCODE(AESMixColumns, T::U128, T::U128 )
A64: Implement AESIMC and AESMC
2018-01-30 12:56:18 +00:00
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
// Vector instructions
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(VectorGetElement8, T::U8, T::U128, T::U8 )
OPCODE(VectorGetElement16, T::U16, T::U128, T::U8 )
OPCODE(VectorGetElement32, T::U32, T::U128, T::U8 )
OPCODE(VectorGetElement64, T::U64, T::U128, T::U8 )
OPCODE(VectorSetElement8, T::U128, T::U128, T::U8, T::U8 )
OPCODE(VectorSetElement16, T::U128, T::U128, T::U8, T::U16 )
OPCODE(VectorSetElement32, T::U128, T::U128, T::U8, T::U32 )
OPCODE(VectorSetElement64, T::U128, T::U128, T::U8, T::U64 )
OPCODE(VectorAdd8, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorAdd64, T::U128, T::U128, T::U128 )
OPCODE(VectorAnd, T::U128, T::U128, T::U128 )
IR: Implement VectorArithmeticShiftRight
2018-02-10 23:27:46 +00:00
OPCODE(VectorArithmeticShiftRight8, T::U128, T::U128, T::U8 )
OPCODE(VectorArithmeticShiftRight16,T::U128, T::U128, T::U8 )
OPCODE(VectorArithmeticShiftRight32,T::U128, T::U128, T::U8 )
OPCODE(VectorArithmeticShiftRight64,T::U128, T::U128, T::U8 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(VectorBroadcastLower8, T::U128, T::U8 )
OPCODE(VectorBroadcastLower16, T::U128, T::U16 )
OPCODE(VectorBroadcastLower32, T::U128, T::U32 )
OPCODE(VectorBroadcast8, T::U128, T::U8 )
OPCODE(VectorBroadcast16, T::U128, T::U16 )
OPCODE(VectorBroadcast32, T::U128, T::U32 )
OPCODE(VectorBroadcast64, T::U128, T::U64 )
OPCODE(VectorEor, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual8, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual16, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual32, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual64, T::U128, T::U128, T::U128 )
OPCODE(VectorEqual128, T::U128, T::U128, T::U128 )
IR: Implement VectorGreaterSigned
2018-02-13 14:06:54 +00:00
OPCODE(VectorGreaterS8, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS16, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS32, T::U128, T::U128, T::U128 )
OPCODE(VectorGreaterS64, T::U128, T::U128, T::U128 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(VectorInterleaveLower8, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower16, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower32, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveLower64, T::U128, T::U128, T::U128 )
IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords I should have added this when I introduced the functions for interleaving low-order equivalents for consistency in the interface.
2018-03-29 21:11:14 +01:00
OPCODE(VectorInterleaveUpper8, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveUpper16, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveUpper32, T::U128, T::U128, T::U128 )
OPCODE(VectorInterleaveUpper64, T::U128, T::U128, T::U128 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(VectorLogicalShiftLeft8, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftLeft16, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftLeft32, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftLeft64, T::U128, T::U128, T::U8 )
IR: Implement VectorLogicalShiftRight
2018-02-10 11:05:22 +00:00
OPCODE(VectorLogicalShiftRight8, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight16, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight32, T::U128, T::U128, T::U8 )
OPCODE(VectorLogicalShiftRight64, T::U128, T::U128, T::U8 )
A64: Implement USHL
2018-02-20 19:48:15 +00:00
OPCODE(VectorLogicalVShift8, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShift16, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShift32, T::U128, T::U128, T::U128 )
OPCODE(VectorLogicalVShift64, T::U128, T::U128, T::U128 )
IR: Implement Vector{Max,Min}{Signed,Unsigned}
2018-02-13 17:56:46 +00:00
OPCODE(VectorMaxS8, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxS16, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxS32, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxS64, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU8, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU16, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU32, T::U128, T::U128, T::U128 )
OPCODE(VectorMaxU64, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS8, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS16, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS32, T::U128, T::U128, T::U128 )
OPCODE(VectorMinS64, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU8, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU16, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU32, T::U128, T::U128, T::U128 )
OPCODE(VectorMinU64, T::U128, T::U128, T::U128 )
IR: Implement VectorMultiply
2018-02-11 10:18:29 +00:00
OPCODE(VectorMultiply8, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply16, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply32, T::U128, T::U128, T::U128 )
OPCODE(VectorMultiply64, T::U128, T::U128, T::U128 )
IR: Implement VectorNarrow
2018-02-10 16:47:36 +00:00
OPCODE(VectorNarrow16, T::U128, T::U128 )
OPCODE(VectorNarrow32, T::U128, T::U128 )
OPCODE(VectorNarrow64, T::U128, T::U128 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(VectorNot, T::U128, T::U128 )
OPCODE(VectorOr, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower8, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower16, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAddLower32, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd8, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd16, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
IR: Implement VectorPopulationCount
2018-02-11 11:43:51 +00:00
OPCODE(VectorPopulationCount, T::U128, T::U128 )
ir: Add IR opcodes for emitting vector shuffles This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes) as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
2018-03-18 00:32:07 +00:00
OPCODE(VectorShuffleHighHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleLowHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleWords, T::U128, T::U128, T::U8 )
IR: Implement VectorSignExtend
2018-02-11 16:24:33 +00:00
OPCODE(VectorSignExtend8, T::U128, T::U128 )
OPCODE(VectorSignExtend16, T::U128, T::U128 )
OPCODE(VectorSignExtend32, T::U128, T::U128 )
OPCODE(VectorSignExtend64, T::U128, T::U128 )
IR: Implement VectorSub
2018-02-10 11:25:50 +00:00
OPCODE(VectorSub8, T::U128, T::U128, T::U128 )
OPCODE(VectorSub16, T::U128, T::U128, T::U128 )
OPCODE(VectorSub32, T::U128, T::U128, T::U128 )
OPCODE(VectorSub64, T::U128, T::U128, T::U128 )
IR: Implement VectorZeroExtend
2018-02-10 10:28:38 +00:00
OPCODE(VectorZeroExtend8, T::U128, T::U128 )
OPCODE(VectorZeroExtend16, T::U128, T::U128 )
OPCODE(VectorZeroExtend32, T::U128, T::U128 )
OPCODE(VectorZeroExtend64, T::U128, T::U128 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(VectorZeroUpper, T::U128, T::U128 )
IR: Add IR instruction ZeroVector
2018-02-20 15:38:32 +00:00
OPCODE(ZeroVector, T::U128, )
A64: Implement ADD (vector, vector)
2018-01-21 17:45:43 +00:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point operations
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(FPAbs32, T::U32, T::U32 )
OPCODE(FPAbs64, T::U64, T::U64 )
OPCODE(FPAdd32, T::U32, T::U32, T::U32 )
OPCODE(FPAdd64, T::U64, T::U64, T::U64 )
OPCODE(FPCompare32, T::NZCVFlags, T::U32, T::U32, T::U1 )
OPCODE(FPCompare64, T::NZCVFlags, T::U64, T::U64, T::U1 )
OPCODE(FPDiv32, T::U32, T::U32, T::U32 )
OPCODE(FPDiv64, T::U64, T::U64, T::U64 )
IR: Implement FPMax, FPMin
2018-02-11 16:43:47 +00:00
OPCODE(FPMax32, T::U32, T::U32, T::U32 )
OPCODE(FPMax64, T::U64, T::U64, T::U64 )
A64: Implement FMAXNM (scalar)
2018-02-20 14:05:14 +00:00
OPCODE(FPMaxNumeric32, T::U32, T::U32, T::U32 )
OPCODE(FPMaxNumeric64, T::U64, T::U64, T::U64 )
IR: Implement FPMax, FPMin
2018-02-11 16:43:47 +00:00
OPCODE(FPMin32, T::U32, T::U32, T::U32 )
OPCODE(FPMin64, T::U64, T::U64, T::U64 )
A64: Implement FMINNM (scalar)
2018-02-20 14:08:46 +00:00
OPCODE(FPMinNumeric32, T::U32, T::U32, T::U32 )
OPCODE(FPMinNumeric64, T::U64, T::U64, T::U64 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(FPMul32, T::U32, T::U32, T::U32 )
OPCODE(FPMul64, T::U64, T::U64, T::U64 )
OPCODE(FPNeg32, T::U32, T::U32 )
OPCODE(FPNeg64, T::U64, T::U64 )
OPCODE(FPSqrt32, T::U32, T::U32 )
OPCODE(FPSqrt64, T::U64, T::U64 )
OPCODE(FPSub32, T::U32, T::U32, T::U32 )
OPCODE(FPSub64, T::U64, T::U64, T::U64 )
VFP: Implement VADD.{F32,F64}
2016-08-06 17:21:29 +01:00
Implement VCVT
2016-08-23 22:04:46 +01:00
// Floating-point conversions
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
OPCODE(FPSingleToDouble, T::U64, T::U32 )
OPCODE(FPDoubleToSingle, T::U32, T::U64 )
OPCODE(FPSingleToU32, T::U32, T::U32, T::U1 )
OPCODE(FPSingleToS32, T::U32, T::U32, T::U1 )
OPCODE(FPDoubleToU32, T::U32, T::U64, T::U1 )
OPCODE(FPDoubleToS32, T::U32, T::U64, T::U1 )
OPCODE(FPU32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPS32ToSingle, T::U32, T::U32, T::U1 )
OPCODE(FPU32ToDouble, T::U64, T::U32, T::U1 )
OPCODE(FPS32ToDouble, T::U64, T::U32, T::U1 )
Implement VCVT
2016-08-23 22:04:46 +01:00
IR: Implement FPVectorSub
2018-02-11 12:17:53 +00:00
// Floating-point vector instructions
IR: Implement FPVectorAdd
2018-02-11 16:29:48 +00:00
OPCODE(FPVectorAdd32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorAdd64, T::U128, T::U128, T::U128 )
A64: Implement FDIV (vector)
2018-02-21 14:07:31 +00:00
OPCODE(FPVectorDiv32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorDiv64, T::U128, T::U128, T::U128 )
IR: Implement FPVectorSub
2018-02-11 12:17:53 +00:00
OPCODE(FPVectorSub32, T::U128, T::U128, T::U128 )
OPCODE(FPVectorSub64, T::U128, T::U128, T::U128 )
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
// A32 Memory access
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
A32OPC(ClearExclusive, T::Void, )
A32OPC(SetExclusive, T::Void, T::U32, T::U8 )
A32OPC(ReadMemory8, T::U8, T::U32 )
A32OPC(ReadMemory16, T::U16, T::U32 )
A32OPC(ReadMemory32, T::U32, T::U32 )
A32OPC(ReadMemory64, T::U64, T::U32 )
A32OPC(WriteMemory8, T::Void, T::U32, T::U8 )
A32OPC(WriteMemory16, T::Void, T::U32, T::U16 )
A32OPC(WriteMemory32, T::Void, T::U32, T::U32 )
A32OPC(WriteMemory64, T::Void, T::U32, T::U64 )
A32OPC(ExclusiveWriteMemory8, T::U32, T::U32, T::U8 )
A32OPC(ExclusiveWriteMemory16, T::U32, T::U32, T::U16 )
A32OPC(ExclusiveWriteMemory32, T::U32, T::U32, T::U32 )
A32OPC(ExclusiveWriteMemory64, T::U32, T::U32, T::U32, T::U32 )
Implement coprocessor-related microinstructions * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords
2016-12-31 11:17:47 +00:00
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
// A64 Memory access
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
A64OPC(ClearExclusive, T::Void, )
A64OPC(SetExclusive, T::Void, T::U64, T::U8 )
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
A64OPC(ReadMemory8, T::U8, T::U64 )
A64OPC(ReadMemory16, T::U16, T::U64 )
A64OPC(ReadMemory32, T::U32, T::U64 )
A64OPC(ReadMemory64, T::U64, T::U64 )
A64OPC(ReadMemory128, T::U128, T::U64 )
A64OPC(WriteMemory8, T::Void, T::U64, T::U8 )
A64OPC(WriteMemory16, T::Void, T::U64, T::U16 )
A64OPC(WriteMemory32, T::Void, T::U64, T::U32 )
A64OPC(WriteMemory64, T::Void, T::U64, T::U64 )
A64OPC(WriteMemory128, T::Void, T::U64, T::U128 )
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
2018-02-13 00:19:04 +00:00
A64OPC(ExclusiveWriteMemory8, T::U32, T::U64, T::U8 )
A64OPC(ExclusiveWriteMemory16, T::U32, T::U64, T::U16 )
A64OPC(ExclusiveWriteMemory32, T::U32, T::U64, T::U32 )
A64OPC(ExclusiveWriteMemory64, T::U32, T::U64, T::U64 )
A64OPC(ExclusiveWriteMemory128, T::U32, T::U64, T::U128 )
A32: Implement load stores (immediate)
2018-01-10 01:13:23 +00:00
Implement coprocessor-related microinstructions * CoprocInternalOperation * CoprocSendOneWord * CoprocSendTwoWords * CoprocGetOneWord * CoprocGetTwoWords * CoprocLoadWords * CoprocStoreWords
2016-12-31 11:17:47 +00:00
// Coprocessor
IR: Implement VectorLogicalShiftLeft{8,16,32,64}
2018-02-10 09:31:50 +00:00
A32OPC(CoprocInternalOperation, T::Void, T::CoprocInfo )
A32OPC(CoprocSendOneWord, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocSendTwoWords, T::Void, T::CoprocInfo, T::U32, T::U32 )
A32OPC(CoprocGetOneWord, T::U32, T::CoprocInfo )
A32OPC(CoprocGetTwoWords, T::U64, T::CoprocInfo )
A32OPC(CoprocLoadWords, T::Void, T::CoprocInfo, T::U32 )
A32OPC(CoprocStoreWords, T::Void, T::CoprocInfo, T::U32 )
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