2016-07-01 14:01:06 +01:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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2016-07-07 10:53:09 +01:00
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#include "common/assert.h"
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2016-09-03 21:48:03 +01:00
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#include "frontend/ir/ir_emitter.h"
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#include "frontend/ir/opcodes.h"
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2016-07-01 14:01:06 +01:00
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namespace Dynarmic {
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2016-08-25 17:36:42 +01:00
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namespace IR {
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2016-07-01 14:01:06 +01:00
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void IREmitter::Unimplemented() {
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}
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2016-07-11 22:43:53 +01:00
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u32 IREmitter::PC() {
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2016-08-01 20:03:13 +01:00
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u32 offset = current_location.TFlag() ? 4 : 8;
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return current_location.PC() + offset;
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2016-07-11 22:43:53 +01:00
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}
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u32 IREmitter::AlignPC(size_t alignment) {
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u32 pc = PC();
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return static_cast<u32>(pc - pc % alignment);
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Imm1(bool imm1) {
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return Value(imm1);
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2016-07-08 10:09:18 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Imm8(u8 imm8) {
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return Value(imm8);
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Imm32(u32 imm32) {
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return Value(imm32);
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2016-07-08 10:09:18 +01:00
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}
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2016-12-03 11:29:50 +00:00
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Value IREmitter::Imm64(u64 imm64) {
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return Value(imm64);
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::GetRegister(Arm::Reg reg) {
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if (reg == Arm::Reg::PC) {
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2016-07-11 22:43:53 +01:00
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return Imm32(PC());
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2016-07-08 10:09:18 +01:00
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}
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2016-08-25 17:36:42 +01:00
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return Inst(Opcode::GetRegister, { Value(reg) });
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::GetExtendedRegister(Arm::ExtReg reg) {
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2016-09-07 12:08:35 +01:00
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if (Arm::IsSingleExtReg(reg)) {
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2016-08-25 17:36:42 +01:00
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return Inst(Opcode::GetExtendedRegister32, {Value(reg)});
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2016-09-07 12:08:35 +01:00
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}
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if (Arm::IsDoubleExtReg(reg)) {
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2016-08-25 17:36:42 +01:00
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return Inst(Opcode::GetExtendedRegister64, {Value(reg)});
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2016-08-05 18:54:19 +01:00
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}
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2016-09-07 12:08:35 +01:00
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ASSERT_MSG(false, "Invalid reg.");
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::SetRegister(const Arm::Reg reg, const Value& value) {
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ASSERT(reg != Arm::Reg::PC);
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Inst(Opcode::SetRegister, { Value(reg), value });
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::SetExtendedRegister(const Arm::ExtReg reg, const Value& value) {
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2016-09-07 12:08:35 +01:00
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if (Arm::IsSingleExtReg(reg)) {
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2016-08-25 17:36:42 +01:00
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Inst(Opcode::SetExtendedRegister32, {Value(reg), value});
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2016-09-07 12:08:35 +01:00
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} else if (Arm::IsDoubleExtReg(reg)) {
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2016-08-25 17:36:42 +01:00
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Inst(Opcode::SetExtendedRegister64, {Value(reg), value});
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2016-08-05 18:54:19 +01:00
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} else {
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ASSERT_MSG(false, "Invalid reg.");
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}
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::ALUWritePC(const Value& value) {
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2016-07-08 10:09:18 +01:00
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// This behaviour is ARM version-dependent.
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2016-07-12 10:58:14 +01:00
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// The below implementation is for ARMv6k
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2016-07-18 21:04:39 +01:00
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BranchWritePC(value);
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::BranchWritePC(const Value& value) {
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2016-08-01 20:03:13 +01:00
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if (!current_location.TFlag()) {
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2016-07-12 10:58:14 +01:00
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auto new_pc = And(value, Imm32(0xFFFFFFFC));
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2016-08-25 17:36:42 +01:00
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Inst(Opcode::SetRegister, { Value(Arm::Reg::PC), new_pc });
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2016-07-12 10:58:14 +01:00
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} else {
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auto new_pc = And(value, Imm32(0xFFFFFFFE));
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2016-08-25 17:36:42 +01:00
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Inst(Opcode::SetRegister, { Value(Arm::Reg::PC), new_pc });
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2016-07-12 10:58:14 +01:00
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}
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::BXWritePC(const Value& value) {
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Inst(Opcode::BXWritePC, {value});
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2016-07-18 21:04:39 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::LoadWritePC(const Value& value) {
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2016-07-12 10:58:14 +01:00
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// This behaviour is ARM version-dependent.
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// The below implementation is for ARMv6k
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2016-07-18 21:04:39 +01:00
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BXWritePC(value);
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2016-07-08 10:09:18 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::CallSupervisor(const Value& value) {
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Inst(Opcode::CallSupervisor, {value});
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2016-07-14 14:04:43 +01:00
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}
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2016-09-05 11:54:09 +01:00
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void IREmitter::PushRSB(const LocationDescriptor& return_location) {
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2016-08-25 17:36:42 +01:00
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Inst(Opcode::PushRSB, {Value(return_location.UniqueHash())});
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2016-08-13 00:10:23 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::GetCpsr() {
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return Inst(Opcode::GetCpsr, {});
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2016-08-14 19:39:16 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::SetCpsr(const Value& value) {
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Inst(Opcode::SetCpsr, {value});
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2016-08-14 19:39:16 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::GetCFlag() {
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return Inst(Opcode::GetCFlag, {});
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::SetNFlag(const Value& value) {
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Inst(Opcode::SetNFlag, {value});
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::SetZFlag(const Value& value) {
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Inst(Opcode::SetZFlag, {value});
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::SetCFlag(const Value& value) {
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Inst(Opcode::SetCFlag, {value});
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::SetVFlag(const Value& value) {
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Inst(Opcode::SetVFlag, {value});
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2016-07-08 10:09:18 +01:00
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}
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2016-08-25 17:36:42 +01:00
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void IREmitter::OrQFlag(const Value& value) {
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Inst(Opcode::OrQFlag, {value});
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2016-11-23 19:44:27 +00:00
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}
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Value IREmitter::GetGEFlags() {
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return Inst(Opcode::GetGEFlags, {});
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}
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void IREmitter::SetGEFlags(const Value& value) {
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Inst(Opcode::SetGEFlags, {value});
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2016-08-06 22:04:52 +01:00
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}
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2016-08-26 22:47:54 +01:00
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Value IREmitter::GetFpscr() {
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return Inst(Opcode::GetFpscr, {});
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}
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void IREmitter::SetFpscr(const Value& new_fpscr) {
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Inst(Opcode::SetFpscr, {new_fpscr});
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}
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Value IREmitter::GetFpscrNZCV() {
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return Inst(Opcode::GetFpscrNZCV, {});
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}
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void IREmitter::SetFpscrNZCV(const Value& new_fpscr_nzcv) {
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Inst(Opcode::SetFpscrNZCV, {new_fpscr_nzcv});
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}
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Value IREmitter::Pack2x32To1x64(const Value& lo, const Value& hi) {
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2016-08-25 17:36:42 +01:00
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return Inst(Opcode::Pack2x32To1x64, {lo, hi});
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2016-08-04 22:04:42 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::LeastSignificantWord(const Value& value) {
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return Inst(Opcode::LeastSignificantWord, {value});
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2016-08-04 22:04:42 +01:00
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}
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarry IREmitter::MostSignificantWord(const Value& value) {
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auto result = Inst(Opcode::MostSignificantWord, {value});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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2016-08-06 21:03:57 +01:00
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return {result, carry_out};
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2016-08-04 22:04:42 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::LeastSignificantHalf(const Value& value) {
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return Inst(Opcode::LeastSignificantHalf, {value});
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2016-07-11 23:06:35 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::LeastSignificantByte(const Value& value) {
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return Inst(Opcode::LeastSignificantByte, {value});
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::MostSignificantBit(const Value& value) {
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return Inst(Opcode::MostSignificantBit, {value});
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::IsZero(const Value& value) {
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return Inst(Opcode::IsZero, {value});
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2016-07-01 14:01:06 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::IsZero64(const Value& value) {
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return Inst(Opcode::IsZero64, {value});
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2016-08-04 22:04:42 +01:00
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}
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarry IREmitter::LogicalShiftLeft(const Value& value_in, const Value& shift_amount, const Value& carry_in) {
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auto result = Inst(Opcode::LogicalShiftLeft, {value_in, shift_amount, carry_in});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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2016-07-01 14:01:06 +01:00
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return {result, carry_out};
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}
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarry IREmitter::LogicalShiftRight(const Value& value_in, const Value& shift_amount, const Value& carry_in) {
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auto result = Inst(Opcode::LogicalShiftRight, {value_in, shift_amount, carry_in});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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2016-07-01 14:01:06 +01:00
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return {result, carry_out};
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::LogicalShiftRight64(const Value& value_in, const Value& shift_amount) {
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return Inst(Opcode::LogicalShiftRight64, {value_in, shift_amount});
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2016-08-07 14:23:33 +01:00
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}
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarry IREmitter::ArithmeticShiftRight(const Value& value_in, const Value& shift_amount, const Value& carry_in) {
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auto result = Inst(Opcode::ArithmeticShiftRight, {value_in, shift_amount, carry_in});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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2016-07-04 10:22:11 +01:00
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return {result, carry_out};
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}
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2016-07-01 14:01:06 +01:00
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarry IREmitter::RotateRight(const Value& value_in, const Value& shift_amount, const Value& carry_in) {
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auto result = Inst(Opcode::RotateRight, {value_in, shift_amount, carry_in});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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2016-07-10 01:18:17 +01:00
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return {result, carry_out};
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}
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarry IREmitter::RotateRightExtended(const Value& value_in, const Value& carry_in) {
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auto result = Inst(Opcode::RotateRightExtended, {value_in, carry_in});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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2016-07-31 19:07:35 +01:00
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return {result, carry_out};
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}
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarryAndOverflow IREmitter::AddWithCarry(const Value& a, const Value& b, const Value& carry_in) {
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auto result = Inst(Opcode::AddWithCarry, {a, b, carry_in});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
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2016-07-08 10:09:18 +01:00
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return {result, carry_out, overflow};
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Add(const Value& a, const Value& b) {
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return Inst(Opcode::AddWithCarry, {a, b, Imm1(0)});
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2016-07-11 22:43:53 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Add64(const Value& a, const Value& b) {
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return Inst(Opcode::Add64, {a, b});
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2016-08-04 22:04:42 +01:00
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}
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2016-08-25 17:36:42 +01:00
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IREmitter::ResultAndCarryAndOverflow IREmitter::SubWithCarry(const Value& a, const Value& b, const Value& carry_in) {
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2016-07-08 11:49:30 +01:00
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// This is equivalent to AddWithCarry(a, Not(b), carry_in).
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2016-08-25 17:36:42 +01:00
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auto result = Inst(Opcode::SubWithCarry, {a, b, carry_in});
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auto carry_out = Inst(Opcode::GetCarryFromOp, {result});
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auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
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2016-07-08 11:49:30 +01:00
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return {result, carry_out, overflow};
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Sub(const Value& a, const Value& b) {
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return Inst(Opcode::SubWithCarry, {a, b, Imm1(1)});
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2016-07-18 15:11:16 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Sub64(const Value& a, const Value& b) {
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return Inst(Opcode::Sub64, {a, b});
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2016-08-06 06:09:47 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Mul(const Value& a, const Value& b) {
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return Inst(Opcode::Mul, {a, b});
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2016-08-04 22:04:42 +01:00
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}
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2016-08-25 17:36:42 +01:00
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Value IREmitter::Mul64(const Value& a, const Value& b) {
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return Inst(Opcode::Mul64, {a, b});
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2016-08-04 22:04:42 +01:00
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}
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|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::And(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::And, {a, b});
|
2016-07-08 10:43:28 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::Eor(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::Eor, {a, b});
|
2016-07-08 11:14:50 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::Or(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::Or, {a, b});
|
2016-07-10 02:06:38 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::Not(const Value& a) {
|
|
|
|
return Inst(Opcode::Not, {a});
|
2016-07-10 03:44:45 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::SignExtendWordToLong(const Value& a) {
|
|
|
|
return Inst(Opcode::SignExtendWordToLong, {a});
|
2016-08-04 22:04:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::SignExtendHalfToWord(const Value& a) {
|
|
|
|
return Inst(Opcode::SignExtendHalfToWord, {a});
|
2016-07-16 19:23:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::SignExtendByteToWord(const Value& a) {
|
|
|
|
return Inst(Opcode::SignExtendByteToWord, {a});
|
2016-07-16 19:23:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ZeroExtendWordToLong(const Value& a) {
|
|
|
|
return Inst(Opcode::ZeroExtendWordToLong, {a});
|
2016-07-16 19:23:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ZeroExtendHalfToWord(const Value& a) {
|
|
|
|
return Inst(Opcode::ZeroExtendHalfToWord, {a});
|
2016-07-16 19:23:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ZeroExtendByteToWord(const Value& a) {
|
|
|
|
return Inst(Opcode::ZeroExtendByteToWord, {a});
|
2016-07-16 19:23:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ByteReverseWord(const Value& a) {
|
|
|
|
return Inst(Opcode::ByteReverseWord, {a});
|
2016-07-16 19:23:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ByteReverseHalf(const Value& a) {
|
|
|
|
return Inst(Opcode::ByteReverseHalf, {a});
|
2016-07-16 19:23:42 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ByteReverseDual(const Value& a) {
|
|
|
|
return Inst(Opcode::ByteReverseDual, {a});
|
2016-07-20 15:34:17 +01:00
|
|
|
}
|
2016-07-16 19:23:42 +01:00
|
|
|
|
2016-12-15 22:33:20 +00:00
|
|
|
Value IREmitter::CountLeadingZeros(const Value& a) {
|
|
|
|
return Inst(Opcode::CountLeadingZeros, {a});
|
2016-12-18 16:25:41 +00:00
|
|
|
}
|
|
|
|
|
2016-12-15 22:33:20 +00:00
|
|
|
IREmitter::ResultAndOverflow IREmitter::SignedSaturatedAdd(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::SignedSaturatedAdd, {a, b});
|
|
|
|
auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
|
|
|
|
return {result, overflow};
|
|
|
|
}
|
|
|
|
|
|
|
|
IREmitter::ResultAndOverflow IREmitter::SignedSaturatedSub(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::SignedSaturatedSub, {a, b});
|
|
|
|
auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
|
|
|
|
return {result, overflow};
|
|
|
|
}
|
|
|
|
|
2016-12-21 14:16:48 +00:00
|
|
|
IREmitter::ResultAndOverflow IREmitter::UnsignedSaturation(const Value& a, size_t bit_size_to_saturate_to) {
|
|
|
|
ASSERT(bit_size_to_saturate_to <= 31);
|
|
|
|
auto result = Inst(Opcode::UnsignedSaturation, {a, Imm8(static_cast<u8>(bit_size_to_saturate_to))});
|
|
|
|
auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
|
|
|
|
return {result, overflow};
|
|
|
|
}
|
|
|
|
|
|
|
|
IREmitter::ResultAndOverflow IREmitter::SignedSaturation(const Value& a, size_t bit_size_to_saturate_to) {
|
|
|
|
ASSERT(bit_size_to_saturate_to >= 1 && bit_size_to_saturate_to <= 32);
|
|
|
|
auto result = Inst(Opcode::SignedSaturation, {a, Imm8(static_cast<u8>(bit_size_to_saturate_to))});
|
|
|
|
auto overflow = Inst(Opcode::GetOverflowFromOp, {result});
|
|
|
|
return {result, overflow};
|
|
|
|
}
|
|
|
|
|
2016-12-04 20:52:33 +00:00
|
|
|
IREmitter::ResultAndGE IREmitter::PackedAddU8(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedAddU8, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
2016-12-18 16:25:41 +00:00
|
|
|
IREmitter::ResultAndGE IREmitter::PackedAddS8(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedAddS8, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
|
|
|
IREmitter::ResultAndGE IREmitter::PackedAddU16(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedAddU16, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
|
|
|
IREmitter::ResultAndGE IREmitter::PackedAddS16(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedAddS16, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
2016-12-05 00:27:59 +00:00
|
|
|
IREmitter::ResultAndGE IREmitter::PackedSubU8(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedSubU8, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
2016-12-18 16:25:41 +00:00
|
|
|
IREmitter::ResultAndGE IREmitter::PackedSubS8(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedSubS8, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
|
|
|
IREmitter::ResultAndGE IREmitter::PackedSubU16(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedSubU16, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
|
|
|
IREmitter::ResultAndGE IREmitter::PackedSubS16(const Value& a, const Value& b) {
|
|
|
|
auto result = Inst(Opcode::PackedSubS16, {a, b});
|
|
|
|
auto ge = Inst(Opcode::GetGEFromOp, {result});
|
|
|
|
return {result, ge};
|
|
|
|
}
|
|
|
|
|
2016-11-25 20:32:22 +00:00
|
|
|
Value IREmitter::PackedHalvingAddU8(const Value& a, const Value& b) {
|
2016-11-26 18:12:29 +00:00
|
|
|
return Inst(Opcode::PackedHalvingAddU8, {a, b});
|
|
|
|
}
|
|
|
|
|
|
|
|
Value IREmitter::PackedHalvingAddS8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedHalvingAddS8, {a, b});
|
2016-11-25 20:32:22 +00:00
|
|
|
}
|
|
|
|
|
2016-11-26 18:27:21 +00:00
|
|
|
Value IREmitter::PackedHalvingSubU8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedHalvingSubU8, {a, b});
|
|
|
|
}
|
|
|
|
|
2016-12-22 12:02:24 +00:00
|
|
|
Value IREmitter::PackedHalvingSubS8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedHalvingSubS8, {a, b});
|
|
|
|
}
|
|
|
|
|
2016-11-26 11:28:20 +00:00
|
|
|
Value IREmitter::PackedHalvingAddU16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedHalvingAddU16, {a, b});
|
|
|
|
}
|
|
|
|
|
2016-11-26 18:12:29 +00:00
|
|
|
Value IREmitter::PackedHalvingAddS16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedHalvingAddS16, {a, b});
|
|
|
|
}
|
|
|
|
|
2016-11-26 18:27:21 +00:00
|
|
|
Value IREmitter::PackedHalvingSubU16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedHalvingSubU16, {a, b});
|
|
|
|
}
|
|
|
|
|
2016-12-22 12:02:24 +00:00
|
|
|
Value IREmitter::PackedHalvingSubS16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedHalvingSubS16, {a, b});
|
|
|
|
}
|
|
|
|
|
2016-12-28 21:28:55 +00:00
|
|
|
Value IREmitter::PackedHalvingSubAddU16(const Value& a, const Value& b, bool asx) {
|
|
|
|
return Inst(Opcode::PackedHalvingSubAddU16, {a, b, Imm1(asx)});
|
|
|
|
}
|
|
|
|
|
|
|
|
Value IREmitter::PackedHalvingSubAddS16(const Value& a, const Value& b, bool asx) {
|
|
|
|
return Inst(Opcode::PackedHalvingSubAddS16, {a, b, Imm1(asx)});
|
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedAddU8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedAddU8, {a, b});
|
2016-08-12 18:26:14 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedAddS8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedAddS8, {a, b});
|
2016-08-12 18:26:14 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedSubU8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedSubU8, {a, b});
|
2016-08-12 16:53:16 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedSubS8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedSubS8, {a, b});
|
2016-08-12 18:18:38 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedAddU16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedAddU16, {a, b});
|
2016-08-12 18:42:16 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedAddS16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedAddS16, {a, b});
|
2016-08-12 18:42:16 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedSubU16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedSubU16, {a, b});
|
2016-08-12 18:42:16 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::PackedSaturatedSubS16(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedSaturatedSubS16, {a, b});
|
2016-08-12 18:42:16 +01:00
|
|
|
}
|
|
|
|
|
2016-12-17 19:52:22 +00:00
|
|
|
Value IREmitter::PackedAbsDiffSumS8(const Value& a, const Value& b) {
|
|
|
|
return Inst(Opcode::PackedAbsDiffSumS8, {a, b});
|
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::TransferToFP32(const Value& a) {
|
|
|
|
return Inst(Opcode::TransferToFP32, {a});
|
2016-08-07 19:25:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::TransferToFP64(const Value& a) {
|
|
|
|
return Inst(Opcode::TransferToFP64, {a});
|
2016-08-07 19:25:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::TransferFromFP32(const Value& a) {
|
|
|
|
return Inst(Opcode::TransferFromFP32, {a});
|
2016-08-07 19:25:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::TransferFromFP64(const Value& a) {
|
|
|
|
return Inst(Opcode::TransferFromFP64, {a});
|
2016-08-07 19:25:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPAbs32(const Value& a) {
|
|
|
|
return Inst(Opcode::FPAbs32, {a});
|
2016-08-07 01:27:18 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPAbs64(const Value& a) {
|
|
|
|
return Inst(Opcode::FPAbs64, {a});
|
2016-08-07 01:27:18 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPAdd32(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-06 17:21:29 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPAdd32, {a, b});
|
2016-08-06 17:21:29 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPAdd64(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-06 17:21:29 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPAdd64, {a, b});
|
2016-08-06 17:21:29 +01:00
|
|
|
}
|
|
|
|
|
2016-11-26 11:17:16 +00:00
|
|
|
void IREmitter::FPCompare32(const Value& a, const Value& b, bool quiet, bool fpscr_controlled) {
|
|
|
|
ASSERT(fpscr_controlled);
|
|
|
|
Inst(Opcode::FPCompare32, {a, b, Imm1(quiet)});
|
|
|
|
}
|
|
|
|
|
|
|
|
void IREmitter::FPCompare64(const Value& a, const Value& b, bool quiet, bool fpscr_controlled) {
|
|
|
|
ASSERT(fpscr_controlled);
|
|
|
|
Inst(Opcode::FPCompare64, {a, b, Imm1(quiet)});
|
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPDiv32(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-07 10:56:12 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPDiv32, {a, b});
|
2016-08-07 10:56:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPDiv64(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-07 10:56:12 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPDiv64, {a, b});
|
2016-08-07 10:56:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPMul32(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-07 10:21:14 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPMul32, {a, b});
|
2016-08-07 10:21:14 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPMul64(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-07 10:21:14 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPMul64, {a, b});
|
2016-08-07 10:21:14 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPNeg32(const Value& a) {
|
|
|
|
return Inst(Opcode::FPNeg32, {a});
|
2016-08-07 10:56:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPNeg64(const Value& a) {
|
|
|
|
return Inst(Opcode::FPNeg64, {a});
|
2016-08-07 10:56:12 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPSqrt32(const Value& a) {
|
|
|
|
return Inst(Opcode::FPSqrt32, {a});
|
2016-08-07 12:19:07 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPSqrt64(const Value& a) {
|
|
|
|
return Inst(Opcode::FPSqrt64, {a});
|
2016-08-07 12:19:07 +01:00
|
|
|
}
|
2016-08-07 10:56:12 +01:00
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPSub32(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-07 01:41:25 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPSub32, {a, b});
|
2016-08-07 01:41:25 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPSub64(const Value& a, const Value& b, bool fpscr_controlled) {
|
2016-08-07 01:41:25 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPSub64, {a, b});
|
2016-08-07 01:41:25 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPDoubleToSingle(const Value& a, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPDoubleToSingle, {a});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPSingleToDouble(const Value& a, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPSingleToDouble, {a});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPSingleToS32(const Value& a, bool round_towards_zero, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPSingleToS32, {a, Imm1(round_towards_zero)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPSingleToU32(const Value& a, bool round_towards_zero, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPSingleToU32, {a, Imm1(round_towards_zero)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPDoubleToS32(const Value& a, bool round_towards_zero, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPDoubleToS32, {a, Imm1(round_towards_zero)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPDoubleToU32(const Value& a, bool round_towards_zero, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPDoubleToU32, {a, Imm1(round_towards_zero)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPS32ToSingle(const Value& a, bool round_to_nearest, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPS32ToSingle, {a, Imm1(round_to_nearest)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPU32ToSingle(const Value& a, bool round_to_nearest, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPU32ToSingle, {a, Imm1(round_to_nearest)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPS32ToDouble(const Value& a, bool round_to_nearest, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPS32ToDouble, {a, Imm1(round_to_nearest)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::FPU32ToDouble(const Value& a, bool round_to_nearest, bool fpscr_controlled) {
|
2016-08-23 22:04:46 +01:00
|
|
|
ASSERT(fpscr_controlled);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::FPU32ToDouble, {a, Imm1(round_to_nearest)});
|
2016-08-23 22:04:46 +01:00
|
|
|
}
|
|
|
|
|
2016-09-02 12:17:22 +01:00
|
|
|
void IREmitter::ClearExclusive() {
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::ClearExclusive, {});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
void IREmitter::SetExclusive(const Value& vaddr, size_t byte_size) {
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
ASSERT(byte_size == 1 || byte_size == 2 || byte_size == 4 || byte_size == 8 || byte_size == 16);
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::SetExclusive, {vaddr, Imm8(u8(byte_size))});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ReadMemory8(const Value& vaddr) {
|
|
|
|
return Inst(Opcode::ReadMemory8, {vaddr});
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ReadMemory16(const Value& vaddr) {
|
|
|
|
auto value = Inst(Opcode::ReadMemory16, {vaddr});
|
2016-08-01 20:03:13 +01:00
|
|
|
return current_location.EFlag() ? ByteReverseHalf(value) : value;
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ReadMemory32(const Value& vaddr) {
|
|
|
|
auto value = Inst(Opcode::ReadMemory32, {vaddr});
|
2016-08-01 20:03:13 +01:00
|
|
|
return current_location.EFlag() ? ByteReverseWord(value) : value;
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ReadMemory64(const Value& vaddr) {
|
|
|
|
auto value = Inst(Opcode::ReadMemory64, {vaddr});
|
2016-08-01 20:03:13 +01:00
|
|
|
return current_location.EFlag() ? ByteReverseDual(value) : value;
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
void IREmitter::WriteMemory8(const Value& vaddr, const Value& value) {
|
|
|
|
Inst(Opcode::WriteMemory8, {vaddr, value});
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
void IREmitter::WriteMemory16(const Value& vaddr, const Value& value) {
|
2016-08-01 20:03:13 +01:00
|
|
|
if (current_location.EFlag()) {
|
2016-07-22 23:55:00 +01:00
|
|
|
auto v = ByteReverseHalf(value);
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::WriteMemory16, {vaddr, v});
|
2016-07-22 23:55:00 +01:00
|
|
|
} else {
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::WriteMemory16, {vaddr, value});
|
2016-07-20 15:34:17 +01:00
|
|
|
}
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
void IREmitter::WriteMemory32(const Value& vaddr, const Value& value) {
|
2016-08-01 20:03:13 +01:00
|
|
|
if (current_location.EFlag()) {
|
2016-07-22 23:55:00 +01:00
|
|
|
auto v = ByteReverseWord(value);
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::WriteMemory32, {vaddr, v});
|
2016-07-22 23:55:00 +01:00
|
|
|
} else {
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::WriteMemory32, {vaddr, value});
|
2016-07-20 15:34:17 +01:00
|
|
|
}
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
void IREmitter::WriteMemory64(const Value& vaddr, const Value& value) {
|
2016-08-01 20:03:13 +01:00
|
|
|
if (current_location.EFlag()) {
|
2016-07-22 23:55:00 +01:00
|
|
|
auto v = ByteReverseDual(value);
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::WriteMemory64, {vaddr, v});
|
2016-07-22 23:55:00 +01:00
|
|
|
} else {
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::WriteMemory64, {vaddr, value});
|
2016-07-20 15:34:17 +01:00
|
|
|
}
|
2016-07-11 22:43:53 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ExclusiveWriteMemory8(const Value& vaddr, const Value& value) {
|
|
|
|
return Inst(Opcode::ExclusiveWriteMemory8, {vaddr, value});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ExclusiveWriteMemory16(const Value& vaddr, const Value& value) {
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
if (current_location.EFlag()) {
|
|
|
|
auto v = ByteReverseHalf(value);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::ExclusiveWriteMemory16, {vaddr, v});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
} else {
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::ExclusiveWriteMemory16, {vaddr, value});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ExclusiveWriteMemory32(const Value& vaddr, const Value& value) {
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
if (current_location.EFlag()) {
|
|
|
|
auto v = ByteReverseWord(value);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::ExclusiveWriteMemory32, {vaddr, v});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
} else {
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::ExclusiveWriteMemory32, {vaddr, value});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::ExclusiveWriteMemory64(const Value& vaddr, const Value& value_lo, const Value& value_hi) {
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
if (current_location.EFlag()) {
|
|
|
|
auto vlo = ByteReverseWord(value_lo);
|
|
|
|
auto vhi = ByteReverseWord(value_hi);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::ExclusiveWriteMemory64, {vaddr, vlo, vhi});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
} else {
|
2016-08-25 17:36:42 +01:00
|
|
|
return Inst(Opcode::ExclusiveWriteMemory64, {vaddr, value_lo, value_hi});
|
TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB
2016-08-09 22:48:20 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-05 14:07:27 +01:00
|
|
|
void IREmitter::Breakpoint() {
|
2016-08-25 17:36:42 +01:00
|
|
|
Inst(Opcode::Breakpoint, {});
|
2016-08-05 14:07:27 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
void IREmitter::SetTerm(const Terminal& terminal) {
|
2016-08-25 15:35:50 +01:00
|
|
|
block.SetTerminal(terminal);
|
2016-07-07 10:53:09 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
Value IREmitter::Inst(Opcode op, std::initializer_list<Value> args) {
|
2016-08-25 15:35:50 +01:00
|
|
|
block.AppendNewInst(op, args);
|
2016-08-25 17:36:42 +01:00
|
|
|
return Value(&block.back());
|
2016-07-01 14:01:06 +01:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:36:42 +01:00
|
|
|
} // namespace IR
|
2016-07-01 14:01:06 +01:00
|
|
|
} // namespace Dynarmic
|