MerryMage
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0575e7421b
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1c9804ea07
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A64: Implement FMAXNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e2b9b7c5b0
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IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8698f057d0
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2cb0a699ba
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IR: Implement FPMax, FPMin
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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98c8e7d1af
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IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eae518a338
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IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b9cd345ddc
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IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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303088a51e
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IR: Implement VectorPopulationCount
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b6de612e01
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IR: Implement VectorMultiply
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d3a4e1efe2
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IR: Vector instructions now take esize argument in emitter
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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f6247125c0
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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35a29a9665
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A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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586854117b
|
Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
dd2a6684fe
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IR: Add ConditionalSelectNZCV instruction
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
2409e5d082
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A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
40614202e7
|
A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
ccef85dbb7
|
A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
8931ee346b
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
4be55b8b84
|
A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
429dc24587
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IR: Merge U32 and U64 variants of FP instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
|
ebfc51c609
|
IR: Implement VectorSetElement{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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Lioncash
|
a5c4fbc783
|
A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
|
Lioncash
|
af1384d700
|
A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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Lioncash
|
7ffbebf290
|
A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
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MerryMage
|
e01b500aea
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ir_emitter: Allow the insertion point for new instructions to be set
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2020-04-22 20:46:12 +01:00 |
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Lioncash
|
7734cf1050
|
A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
|
Lioncash
|
67443efb62
|
General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
d5283e46e8
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IR: Implement IR instructions VectorEqual{8,16,32,64,128}
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2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
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e0c12ec2ad
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
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MerryMage
|
285fd22c30
|
IR: Add IR instruction VectorZeroUpper
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2020-04-22 20:44:37 +01:00 |
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FernandoS27
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ab84524806
|
Implemented SDIV and UDIV instructions
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
e00a522cba
|
IR: Add IR instruction VectorGetElement{8,16,32,64}
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
28ccd85e5c
|
IR: Add IR instruction ZeroExtendToQuad
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
793753bf63
|
IR: Implement Vector{Lower,}Broadcast{8,16,32,64}
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
9b0a21915f
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ir_emitted: Remove unimplemented IR instruction Unimplemented
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
eaf545877a
|
IR: Implement Vector{Lower,}PairedAdd{8,16,32,64}
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
c1a25bfc2f
|
A64: Implement MADD and MSUB
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
b612782445
|
opcodes: Add 64-bit CountLeadingZeroes opcode
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2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
4c4efb2213
|
data_processing_register: Clean-up
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
f81d0a2536
|
A64: Implement AND (vector)
|
2020-04-22 20:42:46 +01:00 |
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