Lioncash
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eb2d28d2b1
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emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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6ad1bce5e0
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A64: Implement REV16 (vector)
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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6177c2c63d
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CMakeLists: Add fp_util, macro_util and math_util headers
Allows the headers to show up within IDEs
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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7a66224d9a
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A64: Implement EOR3 and BCAX
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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bc4bde1fbd
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travis: Use yuzu's unicorn fork
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2020-04-22 20:46:15 +01:00 |
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Lioncash
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8e28bea0ac
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externals: Update catch to v2.2.1
Keeps the testing library up to date
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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be5047c7c2
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impl: Update PC when raising exception
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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49cc6d7fad
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A64: Implement FDIV (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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fd075d8d68
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system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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c832cec96d
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Correct FPSR and FPCR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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147284427b
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A64: Implement USHL
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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fd8f4c1195
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A64: Implement UCVTF (vector, integer), scalar variant
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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be57608353
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A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e4697b1676
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A64: Implement system register TPIDR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e3da92024e
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A64: Implement system registers FPCR and FPSR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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9e4e4e9c1d
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A64: Implement system register CNTPCT_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1e15283d00
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A64: Implement system register CTR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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58fbb3ff1b
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A64: Implement NEG (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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710d09471b
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IR: Add IR instruction ZeroVector
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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2721bb5ace
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emit_x64_floating_point: Add maybe_unused to preprocess parameter
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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0575e7421b
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1c9804ea07
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A64: Implement FMAXNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1dfce0894d
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constant_pool: Add frame parameter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bd2b415850
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A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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84f1c9b7f4
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reg_alloc: Only exchange GPRs
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9df3793af0
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A64: Implement DUP (element), scalar variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6541ec064d
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emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2080a51f41
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A64: Implement FMAX (scalar), FMIN (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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44a5b57f2a
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fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eaa1fd36a7
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travis: Switch unicorn repository
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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7c193485e1
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a64/config: Allow NaN emulation accuracy to be set
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a3df46a75a
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a64_emit_x64: Add conf to A64EmitContext
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1311f67b4a
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fuzz_with_unicorn: Explicitly test floating point instructions
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0e157b0198
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A64: Implement FSQRT (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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07520f32c3
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backend_x64: Accurately handle NaNs
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e97581d063
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fuzz_with_unicorn: Print AArch64 disassembly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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01c1e9017e
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T32: Add initial decoder list
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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ccf7df057b
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simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8cebb87d0d
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A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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7f68d556ab
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decoder/a64: Rearrange SIMD two-register misc decoders
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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d5af052f06
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A64: Implement CMGE (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9d85991906
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A64: Implement CMHI, CMHS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e2b9b7c5b0
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IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0df6725f73
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A64: Implement SMAX, SMIN, UMAX, UMIN
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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adb7f5f86f
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A64: Implement CMGT (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f3fa4a042f
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a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9f04f2c892
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Merge branch 'feature/exclusive-mem'
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2020-04-22 20:46:14 +01:00 |
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