Lioncash
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bebe7235ae
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A64: Implement UZP1 and UZP2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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26d77c6f09
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ir: Add opcodes for performing vector deinterleaving
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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d6f9ed47d9
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A64: Implement FNEG (half-precision)
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2020-04-22 20:46:17 +01:00 |
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MerryMage
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2b8bc1d4e1
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README: Add usage example
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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7efbd73bac
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A64: Implement USHL (scalar)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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41f4717f2b
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A64: Implement FNEG (vector)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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ba1cc6366d
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A64: Implement RSUBHN/RSUBHN2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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e41640fe33
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A64: Implement RADDHN/RADDHN2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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b719a6b3f7
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A64: Implement XAR
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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0b1b131ec2
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simd_two_register_misc: Factor out common comparison code
Gets rid of a tiny bit of duplicated code.
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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ed0b84da70
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A64: Implement CMLE (zero)'s vector variant
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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b595a68ffa
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A64: Implement CMTST (vector)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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48c7f8630c
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A64: Implement ADDHN{2} and SUBHN{2}
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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3acd9c9200
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translate: zero extend result in Vpart when storing to lower part of vector
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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87ca63699f
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emit_x64_vector: Emit PMAXUD in EmitVectorMaxU32 on SSE4.1-capable CPUs
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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f17702f608
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emit_x64_vector: Emit PMINUD in EmitVectorMinU32 on SSE4.1-capable CPUs
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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596a8dd1dd
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emit_x64_vector: Emit PMINSD in EmitVectorMinS32 on SSE4.1-capable CPUs
Provides a better alternative to a fallback operation.
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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75fd4eaaaa
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emit_x64_vector: Get rid of some magic numbers in loop bounds
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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7b80ac25eb
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emit_x64_vector: Generify variable shift functions
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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4ec735f707
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A64: Implement CMLE (zero)'s scalar variant
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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6534184df2
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A64: Implement CMLT (zero)'s scalar single/double-precision variant
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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8863c9bb4b
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A64: Implement SHA512H2
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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033b890e25
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A64: Implement SHA512H
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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d1f5b084b4
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A64: Handle S32->F32 case for SCVTF (vector)
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2020-04-22 20:46:17 +01:00 |
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Lioncash
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38fa984b53
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IR: Add opcode for packed word->f32 conversions
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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b8587d8e34
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A64: Implement SHA512SU1
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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44d846045a
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A64: Implement SHA512SU0
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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ca903c1585
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A64: Implement SHA256H and SHA256H2
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2020-04-22 20:46:16 +01:00 |
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MerryMage
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e4237c44eb
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A64: Implement SCVTF (vector, integer), scalar varaint
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2020-04-22 20:46:16 +01:00 |
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MerryMage
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bfba38d0b6
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impl: Reorganize scalar two-register misc instructions
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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ea582b17cc
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A64: Implement SHA256SU1
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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06c5dcaf5e
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simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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0d50d7314b
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A64: Implement CMGE (zero)'s vector variant
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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ab35dc0e78
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A64: Implement MLS (by element)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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1651e60462
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A64: Implement MUL (by element)
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2020-04-22 20:46:16 +01:00 |
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MerryMage
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a86d4093cd
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A64: Implement MLA (by element)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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7f47402609
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A64: Implement ABS (scalar)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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c8eb4528be
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A64: Implement SHA256SU0
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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cd0b71159a
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CMake: Make FindUnicorn introduce a unicorn target
Makes the find module do all the work of properly setting up the target instead of needing to do it in the main CMakeLists file.
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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181c3b0790
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A64: Implement SHA1M
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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47bc97a71b
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A64: Implement SHA1P
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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718f3e9bb4
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A64: Implement scalar variants of CMEQ, CMGT, and CMGE zero comparison instructions
These can trivially use the ScalarCompare helper function.
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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3ad4e547e4
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A64: Implement scalar variant of NEG
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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b4f3051e4b
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simd: Relocate REV16, REV32 and REV64 vector variants to the proper file
These aren't scalar instruction variants.
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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19e276d10f
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A64: Implement CMEQ (register, scalar)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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5b8c9e5146
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A64: Implement CMHS (register, scalar)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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78bb12276a
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A64: Implement CMHI (register, scalar)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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c18b20b8d1
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A64: Implement CMGE (register, scalar)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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755981d0da
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A64: Implement CMGT (register, scalar)
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2020-04-22 20:46:16 +01:00 |
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Lioncash
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da6627124b
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A64: Implement SHA1C
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2020-04-22 20:46:16 +01:00 |
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