Lioncash
|
4f37c0ec5a
|
A64: Implement SM4EKEY
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
3bde3347a5
|
A64: Implement SM4E
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
4dcc7724e0
|
A64: Implement UHADD
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
f8714f7250
|
A64: Implement SHADD
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
e71612d394
|
A64: Implement SSHL (scalar)
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
ef1e69a1e3
|
A64: Implement SSHL (vector)
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
21974ee57e
|
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
Also adds IR opcodes to dispatch said variants
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
cda75e2079
|
A64: Implement CMTST's scalar variant
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
bebe7235ae
|
A64: Implement UZP1 and UZP2
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
d6f9ed47d9
|
A64: Implement FNEG (half-precision)
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
7efbd73bac
|
A64: Implement USHL (scalar)
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
41f4717f2b
|
A64: Implement FNEG (vector)
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
ba1cc6366d
|
A64: Implement RSUBHN/RSUBHN2
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
e41640fe33
|
A64: Implement RADDHN/RADDHN2
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
b719a6b3f7
|
A64: Implement XAR
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
0b1b131ec2
|
simd_two_register_misc: Factor out common comparison code
Gets rid of a tiny bit of duplicated code.
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
ed0b84da70
|
A64: Implement CMLE (zero)'s vector variant
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
b595a68ffa
|
A64: Implement CMTST (vector)
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
48c7f8630c
|
A64: Implement ADDHN{2} and SUBHN{2}
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
3acd9c9200
|
translate: zero extend result in Vpart when storing to lower part of vector
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
4ec735f707
|
A64: Implement CMLE (zero)'s scalar variant
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
6534184df2
|
A64: Implement CMLT (zero)'s scalar single/double-precision variant
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
8863c9bb4b
|
A64: Implement SHA512H2
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
033b890e25
|
A64: Implement SHA512H
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
d1f5b084b4
|
A64: Handle S32->F32 case for SCVTF (vector)
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
b8587d8e34
|
A64: Implement SHA512SU1
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
44d846045a
|
A64: Implement SHA512SU0
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
ca903c1585
|
A64: Implement SHA256H and SHA256H2
|
2020-04-22 20:46:16 +01:00 |
|
MerryMage
|
e4237c44eb
|
A64: Implement SCVTF (vector, integer), scalar varaint
|
2020-04-22 20:46:16 +01:00 |
|
MerryMage
|
bfba38d0b6
|
impl: Reorganize scalar two-register misc instructions
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
ea582b17cc
|
A64: Implement SHA256SU1
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
06c5dcaf5e
|
simd_two_register_misc: Add missing zeroing of the vector for CMGT and CMLT
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
0d50d7314b
|
A64: Implement CMGE (zero)'s vector variant
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
ab35dc0e78
|
A64: Implement MLS (by element)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
1651e60462
|
A64: Implement MUL (by element)
|
2020-04-22 20:46:16 +01:00 |
|
MerryMage
|
a86d4093cd
|
A64: Implement MLA (by element)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
7f47402609
|
A64: Implement ABS (scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
c8eb4528be
|
A64: Implement SHA256SU0
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
181c3b0790
|
A64: Implement SHA1M
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
47bc97a71b
|
A64: Implement SHA1P
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
718f3e9bb4
|
A64: Implement scalar variants of CMEQ, CMGT, and CMGE zero comparison instructions
These can trivially use the ScalarCompare helper function.
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
3ad4e547e4
|
A64: Implement scalar variant of NEG
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
b4f3051e4b
|
simd: Relocate REV16, REV32 and REV64 vector variants to the proper file
These aren't scalar instruction variants.
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
19e276d10f
|
A64: Implement CMEQ (register, scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
5b8c9e5146
|
A64: Implement CMHS (register, scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
78bb12276a
|
A64: Implement CMHI (register, scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
c18b20b8d1
|
A64: Implement CMGE (register, scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
755981d0da
|
A64: Implement CMGT (register, scalar)
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
da6627124b
|
A64: Implement SHA1C
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
3c013bd9f8
|
A64: Implement SLI (scalar)
|
2020-04-22 20:46:16 +01:00 |
|