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376 commits

Author SHA1 Message Date
Lioncash
7ffbebf290 A64: Implement CRC32C 2020-04-22 20:46:12 +01:00
MerryMage
d7044bc751 assert: Use fmt in ASSERT_MSG 2020-04-22 20:46:12 +01:00
MerryMage
6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass 2020-04-22 20:46:12 +01:00
MerryMage
e01b500aea ir_emitter: Allow the insertion point for new instructions to be set 2020-04-22 20:46:12 +01:00
Lioncash
7734cf1050 A64: Implement EXTR 2020-04-22 20:46:12 +01:00
MerryMage
b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
Lioncash
67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage
d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} 2020-04-22 20:44:38 +01:00
Fernando Sahmkow
e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) 2020-04-22 20:44:38 +01:00
MerryMage
94383fd934 microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2020-04-22 20:44:38 +01:00
MerryMage
285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
FernandoS27
ab84524806 Implemented SDIV and UDIV instructions 2020-04-22 20:44:37 +01:00
MerryMage
e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage
e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage
28ccd85e5c IR: Add IR instruction ZeroExtendToQuad 2020-04-22 20:44:37 +01:00
MerryMage
793753bf63 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2020-04-22 20:44:37 +01:00
Lioncash
8ee854232c General: Default constructors and destructors where applicable 2020-04-22 20:44:37 +01:00
Lioncash
d1e4526e1c ir_emitter: Remove unused includes 2020-04-22 20:44:37 +01:00
MerryMage
9b0a21915f ir_emitted: Remove unimplemented IR instruction Unimplemented 2020-04-22 20:44:37 +01:00
MerryMage
eaf545877a IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2020-04-22 20:42:46 +01:00
MerryMage
394bd57bb6 microinstruction: bug: Add missing opcodes 2020-04-22 20:42:46 +01:00
Lioncash
c1a25bfc2f A64: Implement MADD and MSUB 2020-04-22 20:42:46 +01:00
Lioncash
b612782445 opcodes: Add 64-bit CountLeadingZeroes opcode 2020-04-22 20:42:46 +01:00
MerryMage
4c4efb2213 data_processing_register: Clean-up 2020-04-22 20:42:46 +01:00
MerryMage
f81d0a2536 A64: Implement AND (vector) 2020-04-22 20:42:46 +01:00
MerryMage
a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
MerryMage
5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2020-04-22 20:42:46 +01:00
MerryMage
fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage
6395f09f94 IR: Implement Conditional Select 2020-04-22 20:42:45 +01:00
MerryMage
19da68568e A64/translate/branch: bug: Read-after-write error in BLR 2020-04-22 20:42:45 +01:00
MerryMage
ecebe14a01 ir/location_descriptor: Add missing <functional> header for std::hash 2020-04-22 20:42:45 +01:00
MerryMage
c6a091d874 A64: Optimization: Merge interpret blocks 2020-04-22 20:42:45 +01:00
MerryMage
0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage
61125d6dd1 A64/translate: Add TranslateSingleInstruction function 2020-04-22 20:42:45 +01:00
MerryMage
25411da838 A32: Implement load stores (immediate) 2020-04-22 20:42:45 +01:00
MerryMage
68391b0a05 A64: Implement SVC 2020-04-22 20:42:45 +01:00
MerryMage
cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00
MerryMage
e8bcf72ee5 A64: PSTATE access and tests 2020-04-22 20:42:45 +01:00
MerryMage
23f3afe0b3 A64: Implement branch (register) 2020-04-22 20:42:45 +01:00
MerryMage
0641445e51 A64: Implement logical 2020-04-22 20:42:45 +01:00
MerryMage
c09e69bb97 A64: Implement addsub instructions 2020-04-22 20:42:44 +01:00
MerryMage
d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00
MerryMage
e161cf16f5 A64: Initial framework 2020-04-22 20:42:44 +01:00
MerryMage
f61da0b5a9 IR: Compile-time type-checking of IR 2020-04-22 20:39:27 +01:00
MerryMage
44f7f04b5c IR/Value: Rename RegRef and ExtRegRef to A32Reg and A32ExtReg 2020-04-22 20:39:27 +01:00
MerryMage
9d15e0a8e1 Final A32 refactor 2020-04-22 20:39:27 +01:00
MerryMage
8bef20c24d IR: Split off A32 specific opcodes 2020-04-22 20:33:32 +01:00
MerryMage
b1f0cf9278 A32: Split off A32 specific IREmitter 2020-04-22 20:33:32 +01:00
MerryMage
b3c73e2622 Label A32 specific code appropriately 2020-04-22 20:33:30 +01:00
MerryMage
19a7fb8992 jit_state: Split off CPSR.NZCV 2020-04-22 20:26:40 +01:00
MerryMage
311361b409 jit_state: Split off CPSR.{E,T} 
This allows us to improve code-emission for PopRSBHint. We also improve
code emission other terminals at the same time.
 2020-04-22 20:26:40 +01:00
MerryMage
cb119c2f72 emit_x64: Use boost::icl::interval_map to speed up ranged invalidation 2020-04-22 20:26:40 +01:00
MerryMage
7cac9519b0 microinstruction: Remove DecrementRemainingUses 2020-04-22 20:26:12 +01:00
MerryMage
5d72f7048f basic_block: Add inst address and use count to DumpBlock 
This additional output assists with debugging.
 2020-04-22 20:26:12 +01:00
MerryMage
d1e0a29cd9 Implement IR instruction PackedSelect, reimplement SEL 2020-04-22 20:26:07 +01:00
MerryMage
814e378249 VCMP and VCMPE were the other way around 
- This was due to a misunderstanding of what the E in VCMPE means.
- The E refers to an exception being raised when a QNaN is encountered.
- Added unit tests for VCMP{E}
 2020-04-22 20:26:07 +01:00
MerryMage
29471be317 Standardize location of storage-class specifiers: Place at beginning of declarations 
Justification: C99 specifies that doing otherwise is an obsolescent feature.
 2017-09-29 01:23:45 +01:00
MerryMage
523ae542f4 microinstruction: Implement HasAssociatedPseudoOperation 2017-04-04 13:10:50 +01:00
MerryMage
05e97058c3 parallel: Add and Subtract with Exchange improvements 
* Remove asx argument from PackedHalvingSubAdd{U16,S16} IR instruction
* Implement Packed{Halving,}{AddSub,SubAdd}{U16,S16} IR instructions
* Implement SASX, SSAX, UASX, USAX
 2017-03-24 15:56:24 +00:00
Lynn
fd068ed6b8 Ranged cache invalidation 2017-03-20 11:58:25 +00:00
MerryMage
92a01b0cd8 Prefer ASSERT to DEBUG_ASSERT 2017-02-26 23:30:40 +00:00
MerryMage
bbeea72eba ir_opt: Remove redundant shift instructions 2017-02-26 15:28:14 +00:00
MerryMage
4ed8ee7489 microinstruction: Void arguments when invalidating instruction 2017-02-18 21:29:23 +00:00
MerryMage
642ccb0f66 ir/value: Support U16 immediates 2017-01-29 22:58:11 +00:00
MerryMage
5f7ffe0d0b microinstruction: Implement Inst::AreAllArgsImmediates 2017-01-29 22:56:59 +00:00
MerryMage
22804dc6a5 microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const 2017-01-29 22:53:46 +00:00
MerryMage
1d4446cad5 microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith 2017-01-29 22:52:33 +00:00
MerryMage
48693eb6ff Implement coprocessor-related microinstructions 
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
 2017-01-08 14:56:06 +00:00
MerryMage
d8a37e287c IR: Add IR type CoprocInfo 2017-01-08 14:56:06 +00:00
MerryMage
1efd3a764d IR: Remove unused microinstructions NegateLowWord and NegateHighWord 2017-01-05 20:16:39 +00:00
FernandoS27
d5610eb26c Implement UHASX, UHSAX, SHASX and SHSAX (#75) 2016-12-28 21:32:22 +00:00
Fernando Sahmkow
677f62dd6f Implement SHSUB8 and SHSUB16 (#74) 
* Implement IR operations PackedHalvingSubS8 and PackedHalvingSubS16
 2016-12-22 12:02:24 +00:00
MerryMage
6a269a6ebd IR: Add microinstructions UnsignedSaturation and SignedSaturation 2016-12-21 19:51:25 +00:00
FernandoS27
8919265d2c Implement SADD8, SADD16, SSUB8, SSUB16, USUB16 2016-12-20 21:52:38 +00:00
FernandoS27
3f6ecfe245 Implemented USAD8 and USADA8 2016-12-20 21:52:38 +00:00
MerryMage
96e46ba6b5 Implement QADD, QSUB, QDADD, QDSUB 2016-12-15 22:34:29 +00:00
MerryMage
52e1445f43 Implement USUB8 2016-12-05 00:29:15 +00:00
MerryMage
5c1aab1666 Implement CLZ 
Includes tests
 2016-12-04 22:56:33 +00:00
MerryMage
1a1646d962 Implement UADD8 2016-12-04 20:52:33 +00:00
MerryMage
7cad6949e7 IR: Implement new pseudo-operation GetGEFromOp 2016-12-04 20:52:06 +00:00
MerryMage
e166965f3e Implement VCMP 2016-12-03 11:41:09 +00:00
MerryMage
f2fe376fc6 Support 64-bit immediates 2016-12-03 11:29:50 +00:00
Mat M
de1f831d79 microinstruction: Make use_count private (#53) 
Makes the operation a part of the direct interface.
 2016-11-30 21:51:06 +00:00
Merry
0ff8c375af Implement UHSUB8 and UHSUB16 (#48) 2016-11-26 18:27:21 +00:00
Merry
cb17f9a3ed Implement SHADD8 and SHADD16 (#47) 2016-11-26 18:12:29 +00:00
MerryMage
c0c1bb1094 Implemented UHADD16 2016-11-26 11:28:20 +00:00
Yuri Kunde Schlesner
9ec51f74bd libfmt: Update version to current master 2016-11-25 20:47:04 +00:00
Sebastian Valle
4d44474ad4 Implemented the ARM UHADD8 instruction. (#45) 
The x64 implementation uses the SSSE3 instruction PSHUFB.
A non-SSE fallback is provided in case the CPU doesn't support it.
 2016-11-25 20:32:22 +00:00
MerryMage
b6f7b8babd ir: Implement GetGEFlags, SetGEFlags 2016-11-23 19:44:27 +00:00
Mat M
6a2174ebfa Add missing explicit specifiers (#27) 2016-09-07 12:08:48 +01:00
Mat M
6e0f27a500 types: Add helpers for determining single and doubleword extension registers (#26) 2016-09-07 12:08:35 +01:00
Mat M
5bc9ce544f arm_types: Move into arm folder (#25) 2016-09-06 00:52:33 +01:00
Mat M
b40d19c3b7 location_descriptor: Provide operator<< string overload (#24) 2016-09-05 21:31:25 +01:00
Mat M
6d53bb6d7e arm_types: Split out LocationDescriptor (#20) 
This isn't really an ARM-specific type, since it's used to indicate a
Block location.
 2016-09-05 11:54:09 +01:00
Mat M
84336cf29d value: Change Value into a class (#19) 
'struct' is a little bit of a misnomer, considering it has invariants
 2016-09-05 11:53:56 +01:00
Mat M
858796a029 Eliminate variable shadowing warnings with MSVC (#17) 2016-09-04 11:30:57 +01:00
Mat M
7f9a0c3c38 Remove unnecessary explicit includes (#16) 2016-09-03 21:48:03 +01:00
Mat M
a465b2ddbc ir_emitter: Fix typo. ClearExlcusive -> ClearExclusive (#5) 2016-09-02 12:17:22 +01:00
MerryMage
dca3b2f079 Implement VMRS and VMSR 2016-08-26 22:47:54 +01:00
Lioncash
0102951bdd Convert formatting over to fmtlib 2016-08-26 13:13:19 +01:00
MerryMage
4322c0907c microinstruction: Rename FindUseWithOpcode to GetAssociatedPseudoOperation, encapsulate associated variables 2016-08-25 21:08:47 +01:00
MerryMage
30df51c2dc ir_emitter: Should be in the IR namespace, not the Arm namespace 2016-08-25 17:36:42 +01:00
Lioncash
0e12fb6a56 basic_block: Move all variables behind a public interface 2016-08-25 16:14:37 +01:00
MerryMage
dc26afbd7e translate_arm: Translate more than one conditional instruction in a block 2016-08-25 13:05:33 +01:00
MerryMage
aa9b63bac4 basic_block: DumpBlock now dumps terminal details 2016-08-25 13:01:32 +01:00
Lioncash
eba3a06d80 frontend: Introduce FPSCR register helper class 
Encapsulates all of the FPSCR state.
 2016-08-24 20:51:14 +01:00
MerryMage
b5a86889cd Implement VCVT 2016-08-23 22:20:04 +01:00
Lioncash
d5805cc6eb intrusive_list: Add size querying 
Since we store pointers and have an interface for iterators
set up, the count is just the distance from the beginning
to the end of the list.

Nice thing is that because of this, basic blocks also get
the ability to have a size count without needing to do anything
directly.
 2016-08-23 19:52:09 +01:00
Lioncash
2180a4be7a basic_block: Use a range-based for loop for iteration 2016-08-23 19:51:01 +01:00
MerryMage
e0f9dead5d microinstruction: Identity's type depends on the type of its argument 2016-08-23 15:48:30 +01:00
MerryMage
8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
Lioncash
47f285249b microinstruction: Introduce convenience informational functions 
Whenever more rigorous optimizations are attempted (or even basic ones),
it's usually helpful to know what overall kind of instruction is being
dealt with, in the event certain classes of instructions may be eligible
for optimization.
 2016-08-22 21:36:48 +01:00
Lioncash
06ec4b5977 microinstruction: Make constructor explicit 2016-08-22 16:01:18 +01:00
Lioncash
1abe881921 basic_block: Add proxy member functions for the instruction list 
Currently basic block kind of acts like a 'dumb struct' which makes things
a little more verbose to write (as opposed to keeping it all in one place,
I guess). It's also a little wonky conceptually, considering a block is
composed of instructions (i.e. 'contains' them).

So providing accessors that make it act more like a container can make working
with algorithms a little nicer. It also makes the API a little more
defined.

Ideally, the list would be only available through a function, but
currently, the pool allocator is exposed, which seems somewhat odd,
considering the block itself should manage its overall allocations
(with placement new, and regular new), rather than putting that
sanitizing directly on the IR emitter (it should just care about emission,
not block state). However, recontaining that can be followed up with,
as it's very trivial to do.
 2016-08-22 13:44:56 +01:00
Lioncash
23d190f7b0 intrusive_list: Support inserters 
Allows std::inserter, std::back_inserter, and std::front_inserter to work
with intrusive lists.
 2016-08-19 20:25:17 +01:00
MerryMage
192a0029be ir/opcodes: Implement IR::AreTypesCompatible 
Type-checking is now occuring in more than one place.
 2016-08-19 01:34:14 +01:00
Tillmann Karras
9782e7da3f verification_pass: show type errors 2016-08-19 01:17:30 +01:00
Lioncash
841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00
MerryMage
7d7ac0af71 Optimization: Make SVC use RSB 2016-08-15 15:02:08 +01:00
MerryMage
e164ede4dc TranslateArm: Implement MRS, MSR (imm), MSR (reg) 2016-08-15 11:50:49 +01:00
MerryMage
960d14d18e Optimization: Implement Return Stack Buffer 2016-08-13 00:10:23 +01:00
bunnei
8e68e6fdd9 TranslateArm: Implement QADD16/QSUB16/UQADD16/UQSUB16. 2016-08-12 19:00:44 +01:00
bunnei
4b09c0d032 TranslateArm: Implement QADD8 and UQADD8. 2016-08-12 19:00:44 +01:00
bunnei
127fbe99cb TranslateArm: Implement QSUB8. 2016-08-12 19:00:44 +01:00
bunnei
86fe29c6d2 TranslateArm: Implement UQSUB8. 2016-08-12 19:00:44 +01:00
MerryMage
1029fd27ce Update documentation (2016-08-12) 2016-08-12 18:17:31 +01:00
MerryMage
8964b38cf9 IR/DumpBlock: Print references to ExtRegs 2016-08-11 17:15:02 +01:00
MerryMage
df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage
2eec43178a IR: Opaque can be of any type 2016-08-09 22:46:44 +01:00
Tillmann Karras
5d26899ac9 Add simplified LogicalShiftRight64 IR opcode 2016-08-08 22:27:05 +01:00
Tillmann Karras
ccb2aa96a5 Add support for the APSR.Q flag 2016-08-08 22:27:04 +01:00
MerryMage
a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage
0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage
3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage
12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage
97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage
ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage
94b99f5949 Common: Add an intrusive list implementation; remove use of boost::intrusive::list. 2016-08-06 22:23:01 +01:00
Tillmann Karras
846d07d7b5 Add Sub64 opcode 2016-08-06 21:17:11 +01:00
Tillmann Karras
b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
Tillmann Karras
01aebcb385 Remove *MulHi wrappers 2016-08-06 21:17:11 +01:00
MerryMage
4d127c19dd Common: Add a memory pool implementation, remove use of boost::pool 2016-08-06 20:41:00 +01:00
MerryMage
4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage
640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} 2016-08-05 19:06:10 +01:00
MerryMage
b4aa01ccf4 Merge remote-tracking branch 'tilkax/master' 2016-08-05 14:14:06 +01:00
MerryMage
01cfaf0286 IR: Properly support Identity in IR::Value 2016-08-05 14:09:10 +01:00
MerryMage
ca40015145 IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint) 2016-08-05 14:07:27 +01:00
Tillmann Karras
3fdc093d10 Add more IR opcodes for multiply instructions 
Pack2x32To1x64, LeastSignificantWord, MostSignificantWord, IsZero64,
Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong
 2016-08-05 02:09:30 +01:00
Tillmann Karras
2488926341 Add IR opcode RotateRightExtended 
to rotate through the carry flag
 2016-08-03 00:47:16 +01:00
MerryMage
deb5e2c10d IR::DumpBlock: Incorrect use of std::map::at 2016-08-02 13:47:05 +01:00
MerryMage
4414ec5bc8 RegAlloc: Allow allocation of XMM registers 2016-08-02 13:46:12 +01:00
MerryMage
93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage
be87038ffd IROpt: Port get/set elimination pass to current IR 2016-08-02 11:51:05 +01:00
MerryMage
51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage
5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage
90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage
e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
MerryMage
f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage
c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage
3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage
07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage
9b2aff166a Implement arm_SVC 2016-07-14 14:29:46 +01:00
MerryMage
7d7751c157 Allow IR blocks to require a cond for block entry. 
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
 2016-07-14 12:52:53 +01:00
MerryMage
09420d190b IR: Implement IR microinstructions ALUWritePC and LoadWritePC 2016-07-12 10:58:14 +01:00
MerryMage
1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage
e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage
d11df9067d Implement thumb1_BIC_reg 2016-07-10 10:44:45 +08:00
MerryMage
98a64a92b1 Implement thumb1_ORR_reg 2016-07-10 09:06:38 +08:00
MerryMage
8145b33882 Implemented thumb1_ROR_reg 2016-07-10 08:18:17 +08:00
MerryMage
92142d5a22 Implement thumb1_SUB_reg 2016-07-08 18:49:30 +08:00
MerryMage
df0c324923 Implement thumb1_EOR_reg 2016-07-08 18:14:54 +08:00
MerryMage
8a0511d297 Implement thumb1_AND_reg 2016-07-08 17:44:53 +08:00
MerryMage
d0b48bfb59 Implement thumb1_ADD_reg_t1 and thumb1_ADD_reg_t2 2016-07-08 17:44:51 +08:00
MerryMage
5711e62419 Implement terminal instructions 2016-07-07 17:53:09 +08:00
MerryMage
14388ea690 Proper implementation of Arm::Translate 2016-07-04 21:37:50 +08:00
MerryMage
d743adf518 Reorganisation, Import Skyeye, This is a mess 2016-07-04 17:22:11 +08:00