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570 commits

Author SHA1 Message Date
Lioncash
6723b00497 A64: Implement USRA (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
d56fa8f735 A64: Implement USHR (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
870e418b0b A64: Implement SHL (scalar) 2020-04-22 20:46:16 +01:00
Lioncash
97f2bea4f2 A64: Implement SM3PARTW1 2020-04-22 20:46:16 +01:00
Lioncash
e268b110f0 simd_sha512: Simplify RAX1 
Now that the vector rotation helpers are in, replace the explicit
shifting with the relevant helper function that does the same thing.

Simply tidies up code; no behavioral changes are made.
 2020-04-22 20:46:16 +01:00
Lioncash
20d2491267 A64: Implement SM3PARTW2 2020-04-22 20:46:16 +01:00
Lioncash
e1b662e90c ir: Add helper functions for vector rotation 2020-04-22 20:46:16 +01:00
Lioncash
8a60a63a8b A64: Implement SM3TT2B 2020-04-22 20:46:16 +01:00
Lioncash
b3d4c02098 A64: Implement SM3TT2A 2020-04-22 20:46:16 +01:00
Lioncash
7fbccabd81 A64: Implement SM3TT1B 2020-04-22 20:46:16 +01:00
Lioncash
769373b3ed A64: Implement SM3TT1A 2020-04-22 20:46:16 +01:00
Lioncash
2d269fdcc7 simd_shift_by_immediate: Merge signed/unsigned helper functions 
Gets rid of a little more code duplication.
 2020-04-22 20:46:16 +01:00
Lioncash
d5461be6b4 A64: Implement SM3SS1 2020-04-22 20:46:16 +01:00
Lioncash
2db032ac83 A64: Implement SRI (vector) 2020-04-22 20:46:16 +01:00
Lioncash
11005cfe26 A64: Implement SLI (vector) 2020-04-22 20:46:16 +01:00
Lioncash
e3d9bf55e7 A64: Implement SRSRA (vector) 2020-04-22 20:46:16 +01:00
Lioncash
bc6016cad7 A64: Implement SRSHR (vector) 2020-04-22 20:46:16 +01:00
MerryMage
6c9c829a08 imm: Add additional bit position checks to Imm::Bits 2020-04-22 20:46:16 +01:00
Lioncash
a2f8cdf0a3 A64: Implement SSUBL/SSUBL2 2020-04-22 20:46:16 +01:00
Lioncash
d456fb85c8 A64: Implement SADDL/SADDL2 2020-04-22 20:46:16 +01:00
Lioncash
5c9e7f328d A64: Implement USUBL/USUBL2 2020-04-22 20:46:16 +01:00
Lioncash
88d70e3b8a A64: Implement UADDL/UADDL2 2020-04-22 20:46:16 +01:00
Lioncash
4b3d70de5f simd_shift_by_immediate: Factor out common code in shift instructions 
Gets rid of partial duplication of the same code for instructions that only have a small behavior difference to them.

e.g. The only difference between SSHR and SSRA is that SSRA adds an accumulator before storing the result.
 2020-04-22 20:46:16 +01:00
Lioncash
56803f5203 A64: Implement URSRA (vector) 2020-04-22 20:46:16 +01:00
Lioncash
8afdf4b23d A64: Implement URSHR (vector) 2020-04-22 20:46:16 +01:00
Lioncash
16613ee066 A64: Implement RSHRN/RSHRN2 2020-04-22 20:46:15 +01:00
Lioncash
937990fd2a A64: Implement SHRN/SHRN2 2020-04-22 20:46:15 +01:00
Lioncash
80e005e5b5 A64/translate: Amend I() to also handle u8 and u16 immediates 
This is necessary for instructions like SRSHR, and other related instructions.
 2020-04-22 20:46:15 +01:00
MerryMage
7969871aa3 A64: Implement FMOV (vector, immediate) and mark other SIMD modified immediate instructions as unallocated 2020-04-22 20:46:15 +01:00
MerryMage
5c95e28ed0 A64: Implement ZIP2 2020-04-22 20:46:15 +01:00
MerryMage
871aefb9a0 decoder/a64: Tweak ordering algorithm 
Ensuring only instruction families are sorted with each other in
the fashion previously devised does not admit a total ordering.
 2020-04-22 20:46:15 +01:00
MerryMage
575590d18d ir_emitter: Remove overloads 
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
 2020-04-22 20:46:15 +01:00
Lioncash
83ff7a43d1 A64: Implement RBIT (vector) 2020-04-22 20:46:15 +01:00
Lioncash
64b1f2d468 ir: Add opcode for reversing bits in a vector 2020-04-22 20:46:15 +01:00
Lioncash
9de60b60bb A64/translate: Amend instruction prototypes erroneously marked as taking Reg 
Makes the prototypes consistent
 2020-04-22 20:46:15 +01:00
Lioncash
cf81f04ed3 A64: Implement RAX1 2020-04-22 20:46:15 +01:00
Lioncash
7bcb1c115a A64: Implement ABS (vector) 2020-04-22 20:46:15 +01:00
Lioncash
e33dcce14a ir: Add opcodes for performing vector absolute values 2020-04-22 20:46:15 +01:00
Lioncash
84d49309b9 A64: Implement USUBW/USUBW2 2020-04-22 20:46:15 +01:00
Lioncash
e20fce6b5a A64: Implement SSUBW/SSUBW2 2020-04-22 20:46:15 +01:00
Lioncash
00af6eeab9 A64: Implement SADDW/SADDW2 2020-04-22 20:46:15 +01:00
MerryMage
78a047f0f9 A64: Implement EXT 2020-04-22 20:46:15 +01:00
MerryMage
3472f371df IR: Implement VectorExtract, VectorExtractLower IR instructions 2020-04-22 20:46:15 +01:00
MerryMage
8bba37089e A64: Implement UADDW 2020-04-22 20:46:15 +01:00
MerryMage
5c47f03888 A64: Implement FMUL (vector) 2020-04-22 20:46:15 +01:00
Lioncash
a6e264c2dd A64: Implement UABA 
Now that we have unsigned absolute difference capabilities, we can just use this to
append onto the result via a vector add.
 2020-04-22 20:46:15 +01:00
Lioncash
c2e7364d3e A64: Implement UABD 2020-04-22 20:46:15 +01:00
Lioncash
ad5cf584ce ir: Add opcodes for performing vector unsigned absolute differences 2020-04-22 20:46:15 +01:00
Lioncash
7780af56e3 ir_emitter: Make immediate member functions const qualified 
These don't modify class state
 2020-04-22 20:46:15 +01:00
Lioncash
701f43d61e IR: Add opcodes for interleaving upper-order bytes/halfwords/words/doublewords 
I should have added this when I introduced the functions for interleaving
low-order equivalents for consistency in the interface.
 2020-04-22 20:46:15 +01:00