MerryMage
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7b03da86c2
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IR: Implement FPVector{Max,Min}
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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ddcff86f9c
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microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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901bd9b4e2
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IR: Implement FPRecipStepFused, FPVectorRecipStepFused
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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939f5f5c7a
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IR: Implement FPVectorRecipEstimate
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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c1dcfe29f7
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IR: Implement FPRecipEstimate
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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04f325a05e
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IR: Implement FPVectorNeg
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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771a4fc20b
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IR: Implement FPVectorMulAdd
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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ecbf9dbae5
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IR: Implement A64OrQC
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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b455b566e7
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A64: Implement UQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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3874cb37e3
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A64: Implement SQXTN (vector)
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2020-04-22 20:46:22 +01:00 |
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MerryMage
|
f020dbe4ed
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A64: Implement SQXTUN
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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6918ef7360
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microinstruction: Reorganize FPSCR related instruction queries
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2020-04-22 20:46:22 +01:00 |
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Lioncash
|
a639fa5534
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microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR()
These were forgotten when the opcodes were added.
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
b2e4c16ef8
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A64: Implement FRSQRTS (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
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MerryMage
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45dc5f74f3
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A64: Implement FRSQRTE (vector), single/double variant
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2020-04-22 20:46:22 +01:00 |
|
MerryMage
|
506e544bfe
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IR: Implement FPRSqrtStepFused
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2020-04-22 20:46:22 +01:00 |
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MerryMage
|
bde58b04d4
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IR: Implement FPRSqrtEstimate
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2020-04-22 20:46:21 +01:00 |
|
Subv
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4606a081c9
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A64: The A64SetTPIDR IR instruction writes to a system register and should not be eliminated by the dead code elimination pass.
Previously this instruction was alway eliminated, resulting in incorrect values for TPIDR_EL0.
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2020-04-22 20:46:21 +01:00 |
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MerryMage
|
e18fca17dc
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A64: Implement FABD in terms of existing IR instructions
Fixes NaN issue. Closes #306.
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2020-04-22 20:46:21 +01:00 |
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MerryMage
|
b228694012
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IR: Implement FPRoundInt
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2020-04-22 20:46:20 +01:00 |
|
MerryMage
|
33fa65de23
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A64: Implement FADDP (vector)
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2020-04-22 20:46:19 +01:00 |
|
MerryMage
|
9dba273a8c
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A64: Implement SADDLP
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2020-04-22 20:46:19 +01:00 |
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MerryMage
|
70ff2d73b5
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A64: Implement UADDLP
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2020-04-22 20:46:19 +01:00 |
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MerryMage
|
caaf36dfd6
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IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64}
This implementation just falls-back to the software floating point implementation.
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2020-04-22 20:46:19 +01:00 |
|
Lioncash
|
4aa4885ba7
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ir: Add opcodes for vector conversion of u32/u64 to floating-point
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2020-04-22 20:46:19 +01:00 |
|
Lioncash
|
7a84b6e8d8
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ir: Add opcodes for converting S64 and U64 to single-precision floating-point values
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2020-04-22 20:46:19 +01:00 |
|
Lioncash
|
3a41465eaf
|
ir: Add opcodes for converting S64 and U64 to double-precision values
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2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
81e572c78c
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ir: Extend FPVectorAbs opcode to also handle 16-bit elements for FP16
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2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
fc731dddae
|
ir: Add opcodes for performing vector absolute floating-point values
This will be usable for implementing FACGE and FACGT
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2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
be354dbfd0
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ir/basic_block: Add missing U16 immediate type to DumpBlock
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2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
8a4f8aed06
|
ir: Add opcode for performing FP vector absolute differences
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2020-04-22 20:46:18 +01:00 |
|
MerryMage
|
8c90fcf58e
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IR: Implement FPMulAdd
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2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
c695da1cf3
|
ir: Add opcode for floating-point GE and GT comparisons
The rest of the comparisons can be implemented in terms of these two
|
2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
5ce187a54e
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ir: Add opcodes for floating-point vector equalities
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2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
bc718c5b28
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ir: Add opcodes for performing rounding halving adds
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2020-04-22 20:46:18 +01:00 |
|
Lioncash
|
1e10017f4b
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ir: Add opcodes for signed absolute differences
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
3f6c529da2
|
ir: Add opcode to perform the vector conversion S64->F64
Unfortunately x86 prior to AVX-512 doesn't really give us any convenient instruction to do the work for us
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
44a5f8095a
|
ir: Add opcodes for performing vector halving subtracts
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
b312d28295
|
ir: Add an opcode for doing an SM4 lookup table query
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
089096948a
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ir: Add opcodes for performing halving adds
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
21974ee57e
|
backend_x64/ir: Amend generic LogicalVShift() template to also handle signed variants
Also adds IR opcodes to dispatch said variants
|
2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
26d77c6f09
|
ir: Add opcodes for performing vector deinterleaving
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2020-04-22 20:46:17 +01:00 |
|
Lioncash
|
38fa984b53
|
IR: Add opcode for packed word->f32 conversions
|
2020-04-22 20:46:16 +01:00 |
|
Lioncash
|
e1b662e90c
|
ir: Add helper functions for vector rotation
|
2020-04-22 20:46:16 +01:00 |
|
MerryMage
|
575590d18d
|
ir_emitter: Remove overloads
Having overloads made explicit casting necesssary for these functions when
using types like UAny.
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
64b1f2d468
|
ir: Add opcode for reversing bits in a vector
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
e33dcce14a
|
ir: Add opcodes for performing vector absolute values
|
2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
3472f371df
|
IR: Implement VectorExtract, VectorExtractLower IR instructions
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
5c47f03888
|
A64: Implement FMUL (vector)
|
2020-04-22 20:46:15 +01:00 |
|
Lioncash
|
ad5cf584ce
|
ir: Add opcodes for performing vector unsigned absolute differences
|
2020-04-22 20:46:15 +01:00 |
|