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Author SHA1 Message Date
Lioncash
887732d8a8 A32: Implement ASIMD VSRI 2020-06-18 11:28:12 -04:00
Lioncash
8b98c91ecc A32: Implement ASIMD VSHL 2020-06-18 11:18:33 -04:00
Lioncash
69c999bc66 A32: Implement ASIMD VRSRA 
Now that we have the accumulation and rounding code in place, VRSRA is
extremely trivial to implement.
 2020-06-18 11:03:39 -04:00
Lioncash
14fdd15199 A32: Implement ASIMD VRSHR 2020-06-18 11:00:45 -04:00
Lioncash
276e0b71dc A32: Implement ASIMD VSRA 2020-06-18 11:00:27 -04:00
Lioncash
054dff7cd5 A32: Implement ASIMD VTST 2020-06-18 15:34:05 +01:00
Lioncash
6c142bc5cc A32: Implement ASIMD VSHR 2020-06-18 10:30:20 -04:00
MerryMage
13367a7efd A64: Match A32 page_table code 
Here we increase the similarity between the A64 and A32 front-ends in terms of their
page_table handling code. In this commit, we:

* Reserve and use r14 as a register to store the page_table pointer.
* Align the code to be more similar in structure.
* Add a conf member to A32EmitContext.
* Remove scratch argument from EmitVAddrLookup.
 2020-06-18 12:22:59 +01:00
Lioncash
08350d06f1 A32: Implement ASIMD VQNEG 2020-06-18 09:49:29 +01:00
Lioncash
f6b665f5a4 A32: Implement ASIMD VQABS 2020-06-18 09:49:29 +01:00
MerryMage
b88c291f81 A32: Detect misaligned memory accesses 
This avoids issues with misaligned memory accesses writing into the next page.
 2020-06-17 17:51:37 +01:00
MerryMage
9f3277540a Merge A32 and A64 exclusive monitors 2020-06-17 10:33:09 +01:00
Lioncash
4b371c0445 A32: Implement ASIMD VREV{16, 32, 64} 2020-06-17 10:21:59 +01:00
Lioncash
6dd2c94095 A32: Implement ASIMD VABS 
Very similar to VNEG in that the only thing that differs is the function
called.
 2020-06-16 22:42:18 +01:00
MerryMage
53422bec46 a64_emit_x64: Reduce code duplication in exclusive memory code 2020-06-16 18:16:33 +01:00
MerryMage
a1c9bb94a8 A32: Add yuzu-specific hacks 2020-06-16 17:54:21 +01:00
MerryMage
2c1a4843ad A32 global exlcusive monitor 2020-06-16 17:54:21 +01:00
MerryMage
58abdcce5b backend/x64/a32_*: Rename config to conf 
Standardize on one name for both a32_* and a64_*.
 2020-06-16 14:56:44 +01:00
MerryMage
7ea521b8bf a32_emit_x64: Change ExclusiveWriteMemory64 to require a single U64 argument 2020-06-16 13:32:50 +01:00
MerryMage
aa341b7eea a32_emit_x64: Make ExclusiveWrite a member function of A32EmitX64 2020-06-16 13:03:17 +01:00
MerryMage
62e04845b1 A64/config: Provide default implementation of MemoryWriteExclusive functions 
Returning false is always safe, because this means the exclusive write has failed.
 2020-06-16 13:00:37 +01:00
MerryMage
34ef5142e3 a32_emit_x64: Specify callback as template argument 
Removes unnecessary switch statement.
 2020-06-16 10:23:51 +01:00
MerryMage
58b2c83944 a32_emit_x64: Reduce mov code duplication in {Read,Write}Memory 2020-06-16 10:14:06 +01:00
Lioncash
aabd0d824d A32: Add immediate creation helper 
Provides the same helper function that exists within the A64 frontend
for creating immediate values.
 2020-06-16 09:54:28 +01:00
Lioncash
93ed3441b7 A32: Implement ASIMD VCLS/VCLZ/VCNT 2020-06-16 09:54:28 +01:00
Lioncash
9b06a938a9 fuzz_arm: Ignore endian bit 
A recent change from Qemu (268b1b3dfbb92a9348406f728a33f39e3d8dcd8)
allows user space modification of the E bit.
 2020-06-16 01:53:21 +01:00
Lioncash
15b3de95e4 A32: Implement VNEG 2020-06-16 01:53:21 +01:00
MerryMage
2796a85096 interface/a32: Remove descriptor argument from Disassemble 2020-06-12 15:27:42 +01:00
MerryMage
3ccc415c52 emit_x64_saturation: Improve codegen for saturated result in EmitSignedSaturation 2020-06-12 15:24:37 +01:00
MerryMage
e953f67201 emit_x64_packed: PackedAbsDiffSumS8: Fix case when bits above the lower 32 bits are not zero 2020-06-12 15:24:09 +01:00
MerryMage
6cf5c78bfa Remove .gitmodules 2020-06-11 15:15:05 +01:00
MerryMage
09867081dc gitignore: Add build-*/ 2020-06-11 15:13:38 +01:00
MerryMage
c4cf0b3e47 exception_handler_posix: Just disable fastmem if initialization fails 2020-06-10 22:52:27 +01:00
MerryMage
55bddc767f backend/x64: Touch PEXT/PDEP code 
* Use pext/pdep where not previously used
* Limit pext/pdep to non-AMD platforms due to slowness on AMD
* Use imul/and as alternatives for AMD and non-BMI2 platforms
 2020-06-10 22:30:22 +01:00
MerryMage
f495018f53 block_of_code: Encapsulate CPU feature detection code 2020-06-09 21:25:57 +01:00
MerryMage
feddf69cb4 emit_x64_crc32: Use same constants 2020-06-06 20:46:09 +01:00
MerryMage
66a356e6cb emit_x64_crc32: Further improvements to codegen 2020-06-06 19:04:20 +01:00
MerryMage
bb203429c6 crc32: Remove unnecessary masking 2020-06-04 20:33:46 +01:00
MerryMage
bcde135c23 emit_x64_crc32: Improve 64-bit PCLMULQDQ implementation of EmitCRC32ISO 
Reduce number of PCLMULQDQs to 3
 2020-06-04 19:23:51 +01:00
MerryMage
0f9c70ff42 emit_x64_crc32: Improve PCLMULQDQ implementation of EmitCRC32ISO 
Remove use of pshufd
 2020-06-03 18:55:58 +01:00
MerryMage
fa6aee434e emit_x64_crc32: PCLMULQDQ implementation of EmitCRC32ISO 2020-06-03 11:16:53 +01:00
MerryMage
b47adaee1d emit_x64_vector: SSSE3 implementation of EmitVectorExtract 2020-06-01 15:41:36 +01:00
MerryMage
f3845cea9a A32: Implement ASIMD VQSUB instruction 2020-05-30 18:19:17 +01:00
MerryMage
16ff880f8f A32: Implement ASIMD VQADD 2020-05-30 16:09:37 +01:00
MerryMage
174fbb74c5 simd_three_same: Use VectorSaturated{Signed,Unsigned}{Add,Sub} in SaturatingArithmeticOperation 2020-05-30 15:55:32 +01:00
MerryMage
4e90754873 IR: Implement VectorSaturated{Signed,Unsigned}{Add,Sub} 2020-05-30 15:55:32 +01:00
MerryMage
3a50d444dc A32: Implement ASIMD VHSUB 2020-05-28 22:29:00 +01:00
MerryMage
205e6c5a56 A32: Implement ASIMD VRHADD 2020-05-28 22:29:00 +01:00
MerryMage
946eb03a3b A32: Implement ASIMD VHADD 2020-05-28 22:29:00 +01:00
MerryMage
f8062345bb asimd_two_regs_misc: Use {Get,Set}Vector 2020-05-28 21:05:30 +01:00