mirrors/dynarmic
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
1725 commits 1 branch 0 tags 34 MiB
Commit graph

926 commits

Author SHA1 Message Date
Lioncash
c99d4b762e A64: Implement single and double-precision vector variant of FSQRT 2020-04-22 20:58:10 +01:00
Lioncash
5cf1478620 frontend/ir: Add opcodes for vector square roots 2020-04-22 20:58:10 +01:00
Lioncash
36027ebef5 frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits() 
This was intended to be added within #437, but was missed
 2020-04-22 20:58:10 +01:00
Merry
40b081438a Merge pull request #439 from lioncash/fcmla 
A64: Implement FCADD and FCMLA
 2020-04-22 20:58:10 +01:00
Merry
d91192681a Merge pull request #438 from lioncash/fmulx 
A64: Implement scalar double/single precision FMULX (by element)
 2020-04-22 20:58:10 +01:00
Lioncash
ed29ef8cca A64: Implement FCMLA 2020-04-22 20:58:10 +01:00
Merry
9f11720a69 Merge pull request #437 from lioncash/frecpx 
A64: Implement FRECPX (single, double precision)
 2020-04-22 20:58:10 +01:00
Lioncash
bdcea0b0dc A64: Implement scalar double/single precision FMULX (by element) 2020-04-22 20:58:10 +01:00
Lioncash
5ce17574f9 A64: Implement FCADD 2020-04-22 20:58:10 +01:00
Merry
34d917f34e Merge pull request #436 from lioncash/no-alloc 
A64: Implement LDNP/STNP
 2020-04-22 20:58:10 +01:00
Lioncash
e44730ba6d A64: Implement FRECPX (single, double precision) 2020-04-22 20:58:10 +01:00
Lioncash
bfaeb08d3c A64: Implement LDNP/STNP 
LDNP and STNP indicate that a memory access is non-temporal/streaming
(i.e. unlikely to be repeated), allowing data caching to not be
performed. However, given this is only a hint, we can treat these two
instructions as regular LDP and STP instructions for the time being.
 2020-04-22 20:58:10 +01:00
Lioncash
9cf3c25811 frontend/ir/ir_emitter: Add opcodes for floating point reciprocal exponents 2020-04-22 20:58:10 +01:00
Lioncash
05a6ab691d translate_arm/coprocessor: Minor tidying up 2020-04-22 20:58:10 +01:00
Lioncash
1e32a09c03 translate_arm/vfp2: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
e209b31073 translate_arm/synchronization: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
9514e3602e translate_arm/status_register_access: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c6aa1a708a translate_arm/saturated: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
a72813599a translate_arm/reversal: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
7be56e6b67 translate_arm/parallel: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
3c00a616d6 translate_arm/packing: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c711188f46 translate_arm/multiply: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
c8dad40d81 translate_arm/misc: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
a7bf5ff77d translate_arm/load_store: Invert conditionals where applicable 2020-04-22 20:58:10 +01:00
Lioncash
f4b19a7393 translate_arm/extension: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
c2de6ecfd0 translate_arm/exception_generating: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
d8a8d3b073 translate_arm/data_processing: Invert conditionals where applicable 2020-04-22 20:58:09 +01:00
Lioncash
df5c51ff47 translate_arm/branch: Invert conditionals where applicable 
Allows unindenting code a bit.
 2020-04-22 20:58:09 +01:00
Lioncash
ee973f13c7 frontend/A32/ir_emitter: Mark PC() and AlignPC() as const-qualified member functions 
These don't modify instance state, so they can be const-qualified member
functions.
 2020-04-22 20:57:38 +01:00
Lioncash
3a2dd09122 frontend/A64/ir_emitter: Mark PC() and AlignPC() as const qualified member functions 
These don't actually alter any instance state.
 2020-04-22 20:57:38 +01:00
MerryMage
e3898e628e A64: Implement FMULX (by element), single and double precision variants 2020-04-22 20:57:37 +01:00
MerryMage
c106d8cedf A64: Implement FMULX, vector single-precision and double-precision variant 2020-04-22 20:57:37 +01:00
MerryMage
fa8925c4df IR: Implement FPVectorMulX 2020-04-22 20:57:37 +01:00
Michał Janiszewski
bbd8abaa25 Provide justification for always-true condition (#412) 2020-04-22 20:57:37 +01:00
V.Kalyuzhny
764a93bf5a Switch boost::optional to std::optional 2020-04-22 20:57:37 +01:00
Lioncash
f1a66c37ba a64: Add ARMv8.4+ instructions encodings to the encoding table 
Keeps the table up to date with the ARM specification.
 2020-04-22 20:57:37 +01:00
Lioncash
0583d401e3 ir/value: Add IsSignedImmediate() and IsUnsignedImmediate() functions to Value's interface 
This allows testing against arbitrary values while also simultaneously
eliminating the need to check IsImmediate() all the time in expressions.
 2020-04-22 20:57:37 +01:00
Lioncash
e3258e8525 ir/value: Add a GetImmediateAsS64() function 
Provides a signed analogue to GetImmediateAsU64() for consistency with
both integral classes when it comes to signed/unsigned..
 2020-04-22 20:57:37 +01:00
Lioncash
4a3c064b15 ir/value: Add an IsZero() member function to Value's interface 
By far, one of the most common things to check for is whether or not a
value is zero, as it typically allows folding away unnecesary
operations (other close contenders that can help with eliding operations  are 1 and -1).

So instead of requiring a check for an immediate and then actually
retrieving the integral value and checking it, we can wrap it within a
function to make it more convenient.
 2020-04-22 20:57:37 +01:00
Merry
c649f11c0a Merge pull request #401 from lioncash/folding 
constant_propagation_pass: Fold &, |, ^, and ~ operations where applicable
 2020-04-22 20:56:01 +01:00
MerryMage
2524d536b0 A32/ir_emitter: Bugfix: ExceptionRaised was producing incorrect PC 
Use actual PC and not pipelined PC.
 2020-04-22 20:56:01 +01:00
Lioncash
d69fceec55 value: Move ImmediateToU64() to be a part of Value's interface 
This'll make it slightly nicer to do basic constant folding for 32-bit
and 64-bit variants of the same IR opcode type. By that, I mean it's
possible to inspect immediate values without a bunch of conditional
checks beforehand to verify that it's possible to call GetU32() or
GetU64, etc.
 2020-04-22 20:55:50 +01:00
Lioncash
f40fcda1f6 ir/value: Add member function to check whether or not all bits of a contained value are set 
This is useful when we wish to know if a contained value is something
like 0xFFFFFFFF, as this helps perform constant folding. For example the
operation: x & 0xFFFFFFFF can be folded to just x in the 32-bit case.
 2020-04-22 20:55:50 +01:00
MerryMage
f0920c0ded Fix VShift terminology 
An arithmetic shift is by definition a signed shift, and a logical shift is by definition an unsigned shift.

- Rename VectorLogicalVShiftS* -> VectorArithmeticVShift*
- Rename VectorLogicalVShiftU* -> VectorLogicalVShift*
 2020-04-22 20:55:50 +01:00
VelocityRa
c30b8dbe99 decoders: Cast to correctly-sized type before shifting 
Fixes decoding for 64-bit instructions

Does not help/apply to any currently supported ARM versions (since
all are 32-bit length or below), it's for future-proofing should
such an arch be supported.
 2020-04-22 20:55:50 +01:00
MerryMage
09bf273bc8 A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant 2020-04-22 20:55:06 +01:00
MerryMage
f9129db6fd A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant 2020-04-22 20:55:06 +01:00
Lioncash
48df9b9a7d A64: Implement UQSHL's vector immediate and register variants 2020-04-22 20:55:06 +01:00
Lioncash
d426dfe942 ir: Add opcodes for unsigned saturating left shifts 2020-04-22 20:55:06 +01:00
Lioncash
ab60720418 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants 
Makes them all consistent, so it isn't necessary to change the
prototypes over when implementing them.
 2020-04-22 20:55:06 +01:00