Lioncash
e4c65721fe
frontend/ir/type: Generify std::array declaration
...
With deduction guides, we can eliminate the need to explicitly size the
array. Also newlines the elements based off their relation, making it
slightly nicer to read.
2020-04-22 21:02:46 +01:00
Lioncash
4ba2318b2e
A32: Replace immediate type aliases with the Imm template
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Replaces type aliases of raw integral types with the more type-safe Imm
template, like how the AArch64 frontend has been using it.
This makes the two frontends more consistent with one another.
2020-04-22 21:02:46 +01:00
Lioncash
f01dc9192a
CMakeLists: Add a namespace to the export
...
Avoids potentially dumping boost, fmt, and xbyak targets into a
top-level namespace without any qualification, which can lead to build
errors in projects that already make use of them.
2020-04-22 21:02:46 +01:00
Lioncash
f96036b3f1
A32/barrier: Correct PC assignment within ISB
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The SetRegister() IR function doesn't allow specifying the PC as a
register. This is a discrepancy that slipped through (my bad). Instead,
we can use BranchWritePC(), like how the other similar PC modifying
locations do it.
2020-04-22 21:02:46 +01:00
Lioncash
196e7b5e35
frontend/A32/ir_emitter: Mark locals as const where applicable
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Makes const usage consistent within the source file.
2020-04-22 21:02:46 +01:00
Lioncash
511613c736
frontend/A32/types: Use helper function in operator+ overload
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Allows deduplicating an assert and a cast.
2020-04-22 21:02:46 +01:00
Lioncash
8103652a91
frontend: Move imm.h to the top-level directory of the frontends
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Preparation to utilize the immediate type within the A32 backend as
well, which will allow eliminating numerous type aliases like Imm4,
Imm5, etc.
2020-04-22 21:02:46 +01:00
Lioncash
796bb8a7f7
frontend/A64/types: Make RegNumber() and VecNumber() constexpr
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Given they simply perform casting, they can be safely made constexpr.
2020-04-22 21:02:46 +01:00
Lioncash
64e51a6d4d
A32/disassembler_arm: Mark utility functions as static where applicable
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These don't depend on class state and can be marked static to make that
explicit.
2020-04-22 21:02:46 +01:00
Lioncash
0c43228ad5
frontend/A64/types: Use helper functions in operator+ overloads
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Allows us to get rid of another explicit cast.
2020-04-22 21:02:46 +01:00
Lioncash
a1cace21a9
frontend/ir/ir_emitter: Apply const to locals where applicable
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Makes const usage consistent with all other functions in the source
file.
2020-04-22 21:02:46 +01:00
Lioncash
0a35836998
frontend/ir/ir_emitter: Use switch constructs in floating point opcodes where applicable
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This'll reduce the amount of noise necessary in changes implementing
half-precision instructions, as the type can just be prepended to the
switch cases, instead of rewriting the whole if/else branch.
2020-04-22 21:02:46 +01:00
Lioncash
8316d231e9
A32: Implement barrier instructions introduced in ARMv7
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Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
2020-04-22 21:02:46 +01:00
Lioncash
7fc3bd689d
A32: Implement ARM-mode MLS
2020-04-22 21:02:46 +01:00
Lioncash
8b338b7def
A32: Implement ARM-mode MOVT
2020-04-22 21:02:46 +01:00
Lioncash
877fa0f8c3
A32: Implement ARM-mode SBFX
2020-04-22 21:02:46 +01:00
Lioncash
47218ee65d
A32: Implement ARM-mode UBFX
2020-04-22 21:02:46 +01:00
Lioncash
2970b34e3c
A32: Implement ARM-mode BFI
2020-04-22 21:02:46 +01:00
Lioncash
fab3a59e05
A32: Implement ARM-mode BFC
2020-04-22 21:02:46 +01:00
Lioncash
7305d13221
A32: Implement ARM-mode RBIT
2020-04-22 21:02:46 +01:00
Lioncash
b2f7a0e7ba
A32: Implement ARM-mode SDIV/UDIV
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Now that we have Unicorn in place, we can freely implement instructions
introduced in newer versions of the ARM architecture.
2020-04-22 21:02:46 +01:00
Lioncash
c0ae23bbb7
A32/translate_thumb: Clean up formatting
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Performs a similar tidying up of the Thumb translator, like what was
done with the regular ARM translator to make it consistent with the rest
of the codebase.
The A32 backend (both Thumb and ARM), will likely see more changes to it
in the near future, so this just acts as a "dusting off".
2020-04-22 21:02:46 +01:00
Merry
837c23a8ec
Merge pull request #483 from lioncash/invert
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frontend/ir/cond: Remove unused invert() function
2020-04-22 21:02:46 +01:00
Lioncash
d12e375481
common/fp/op/FPConvert: Remove unnecessary casts in FPConvert()
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These were made unnecessary in 2c2fdb435cf8e358a0c5b907ce8131e434df3f22,
but were missed during the initial removal.
2020-04-22 21:02:46 +01:00
Merry
09ee64ea98
Merge pull request #482 from lioncash/fixedfp
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A64: Handle half-precision variants of FP->Fixed instructions
2020-04-22 21:02:45 +01:00
MerryMage
1e1e9c17c7
emit_x64_data_processing: Remove INVALID_REG
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INVALID_REG.cvt8() now throws
2020-04-22 21:02:45 +01:00
Lioncash
06ec6ab0da
frontend/ir/cond: Remove unused invert() function
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This is no longer used by anything in the codebase, so it can be
removed.
2020-04-22 21:01:46 +01:00
Merry
d71f51b0da
Merge pull request #481 from lioncash/alloc
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ir/basic_block: Forward declare headers where applicable
2020-04-22 21:01:46 +01:00
Lioncash
64e3d233f4
A64: Handle half-precision variants of FP->Fixed-point instructions
2020-04-22 21:01:45 +01:00
Lioncash
4fc531f71b
ir/basic_block: Forward declare headers where applicable
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Now that the constructor and destructors have been placed within the cpp
file, we can forward declare the memory pool data structures. Now, a
change to the memory pool code won't ripple across the entirety of the
IR emitter.
2020-04-22 21:01:45 +01:00
Lioncash
427b7afd66
frontend/ir/microinstruction: Add missing fixed-point opcodes to ReadsFromAndWritesToFPSRCumulativeExceptionBits()
2020-04-22 21:01:45 +01:00
Lioncash
c9777ef997
common/fp/info: Make half-precision info struct functions return correctly sized types
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While initially done to potentially prevent creating bugs due to C++
having a silly type-promotion mechanism involving types < sizeof(int)
and unsignedness, given that the bulk of these functions' usages
are on exit paths, these can return the correct type to avoid the need
to cast at every usage point.
2020-04-22 21:01:45 +01:00
Lioncash
9309d95b17
ir/block: Default ctor and dtor in the cpp file
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Prevents potentially inlining allocation code everywhere. While we're at
it, also explicitly delete/default the copy/move constructor/assignment
operators to be explicit about them.
2020-04-22 21:01:45 +01:00
Lioncash
604f39f00a
frontend/ir_emitter: Add half-precision->fixed-point opcodes
2020-04-22 21:01:45 +01:00
Lioncash
4ecfbc14de
common/fp/op/FPToFixed: Add half-precision specialization of FPToFixed
2020-04-22 21:01:45 +01:00
Lioncash
471eb77bc9
A64: Implement FRSQRTS' half-precision vector variant
2020-04-22 21:01:45 +01:00
Lioncash
f9b2862217
A64: Implement FRSQRTS' half-precision scalar variant
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With the necessary machinery in place, we can now handle the
half-precision variant.
2020-04-22 21:01:45 +01:00
Lioncash
96356fac93
frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused
2020-04-22 21:01:45 +01:00
Merry
45864133f5
Merge pull request #478 from lioncash/stepfused
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A64: Handle half-precision variants of FRECPE and FRECPS
2020-04-22 21:01:44 +01:00
Lioncash
824c551ba2
frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused
2020-04-22 21:01:44 +01:00
Lioncash
3739d92097
A64: Implement half-precision vector variant of FRECPE
2020-04-22 21:01:44 +01:00
Lioncash
e3b2eb57b5
common/fp/op/FPRSqrtStepFused: Add half-precision specialization for FPRSqrtStepFused
2020-04-22 21:01:44 +01:00
Lioncash
7b212ec8ae
A64: Implement half-precision variant of FRSQRTE's vector variant
2020-04-22 21:01:44 +01:00
Lioncash
0945a491bd
A64: Implement half-precision scalar variant of FRECPE
2020-04-22 21:01:44 +01:00
Lioncash
77c84bcf9b
A64: Implement half-precision variant of FRSQRTE's scalar variant
2020-04-22 21:01:44 +01:00
Lioncash
86b7626a2f
A64: Implement half-precision vector variant of FRECPS
2020-04-22 21:01:44 +01:00
Lioncash
037acb17b9
frontend/ir_emitter: Add half-precision opcode variant for FPVectorRSqrtEstimate
2020-04-22 21:01:44 +01:00
Lioncash
de43f011a7
A64: Implement half-precision scalar variant of FRECPS
2020-04-22 21:01:44 +01:00
Lioncash
5dba99b4f4
frontend/ir_emitter: Add half-precision opcode variant for FPRSqrtEstimate
2020-04-22 21:01:44 +01:00
Lioncash
825a3ea16f
frontend/ir_emitter: Add half-precision opcode for FPVectorRecipEstimate
2020-04-22 21:01:44 +01:00
Lioncash
726b9914c5
common/fp/op/FPRSqrtEstimate: Add half-precision specialization for FPRSqrtEstimate
2020-04-22 21:01:44 +01:00
Lioncash
2184d24e8f
frontend/ir_emitter: Add half-precision opcode for FPRecipEstimate
2020-04-22 21:01:44 +01:00
Lioncash
af2e5afed6
common/fp/op: Add half-precision specialization for FPRecipEstimate
2020-04-22 21:01:44 +01:00
Lioncash
d7f394fc1a
A64: Enable half-precision vector FRINT* variants
2020-04-22 21:01:44 +01:00
Lioncash
5d5c9f149f
frontend/ir_emitter: Add half-precision opcode for FPVectorRecipStepFused
2020-04-22 21:01:44 +01:00
Lioncash
24f583c498
A64: Enable half-precision variants of floating-point FRINT* variants
...
With all the backing machinery in place, we can remove the fallback
check for half-precision.
2020-04-22 21:01:44 +01:00
Lioncash
6da0411111
frontend/ir_emitter: Add half-precision opcode for FPRecipStepFused
2020-04-22 21:01:44 +01:00
Lioncash
fb829b9525
frontend/microinstruction: Add FPVectorRoundInt types to ReadsFromAndWritesToFPSRCumulativeExceptionBits()
...
All variants were previously missing from this.
2020-04-22 21:01:44 +01:00
Lioncash
68d8cd2b13
common/fp/op: Add half-precision specialization for FPRecipStepFused
2020-04-22 21:01:44 +01:00
Lioncash
5b4673da4b
frontend/ir_emitter: Add half-precision variant of FPVectorRoundInt
2020-04-22 21:01:44 +01:00
Lioncash
ad0c698f89
frontend/ir_emitter: Add half-precision variant of FPRoundInt
2020-04-22 21:01:44 +01:00
Lioncash
61cec94a19
fp/op/FPRoundInt: Add half-precision specialization of FPRoundInt
2020-04-22 21:01:44 +01:00
Merry
cb9a1b18b6
Merge pull request #475 from lioncash/muladd
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A64: Enable half-precision variants of floating-point multiply-add instructions
2020-04-22 21:01:44 +01:00
Merry
d6db7ad46c
Merge pull request #474 from lioncash/bracing
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load_store_*: Make bracing consistent and variables const where applicable
2020-04-22 21:01:44 +01:00
Merry
1b6520f5dd
A64/location_descriptor: Ensure FZ16 is included in the FPCR mask
2020-04-22 21:01:44 +01:00
Merry
13f421c27d
Merge pull request #473 from lioncash/sqshlu
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A64: Implement SQSHLU
2020-04-22 21:01:44 +01:00
Lioncash
b5bf890584
load_store_*: Make bracing consistent and variables const where applicable
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Makes bracing consistent, and variables const where applicable to be
consistent with the rest of the codebase.
In most bracing cases, they'd need to be added to conditionals that
would involve checking stack pointer alignment in the future anyways.
2020-04-22 21:01:44 +01:00
Lioncash
9a58c3f1c7
A64: Implement FMLA/FMLS' half-precision vector indexed variants
2020-04-22 21:01:44 +01:00
Merry
d7da53a74b
Merge pull request #472 from lioncash/exception
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general: Mark hash functions as noexcept
2020-04-22 21:01:44 +01:00
Lioncash
9dcc04e106
A64: Implement SQSHLU's scalar variant
2020-04-22 21:01:44 +01:00
Merry
b91c6c8bae
Merge pull request #471 from lioncash/sqrdmulh
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A64: Implement SQRDMULH's scalar vector variant
2020-04-22 21:01:44 +01:00
Lioncash
1fdd3ef8a0
A64: Implement FMLA/FMLS' half-precision scalar indexed variants
2020-04-22 21:01:44 +01:00
Lioncash
2d59d10ac8
A64: Implement SQSHLU's vector variant
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The vector shift by immediate category is now fully implemented.
2020-04-22 21:01:44 +01:00
Merry
b5e25959d9
Merge pull request #470 from lioncash/assert
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general: Replace unreachable-imitating assertions with UNREACHABLE()
2020-04-22 21:01:44 +01:00
Lioncash
d6606deda2
A64: Implement half-precision vector variants of FMLA/FMLS
2020-04-22 21:01:44 +01:00
Lioncash
a4cadf1cd9
frontend/ir_emitter: Add opcodes for signed saturated left shifts with unsigned saturation
2020-04-22 21:01:44 +01:00
Lioncash
ec6b3ae084
ir/frontend: Add half-precision opcode for FPVectorMulAdd
2020-04-22 21:01:44 +01:00
Lioncash
5f74d25bf7
A64: Enable half-precision floating point variants of FP data-processing three register instructions
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This handles half-precision floating point for:
- FMADD
- FMSUB
- FNMADD
- FNMSUB
2020-04-22 21:01:44 +01:00
Lioncash
bd82513199
frontend/ir_emitter: Add half-precision opcode for FPMulAdd
2020-04-22 21:01:44 +01:00
Lioncash
79a892d23c
fp/op/FPMulAdd: Add half-precision floating-point specialization
2020-04-22 21:01:44 +01:00
Lioncash
7bb5440507
general: Mark hash functions as noexcept
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Generally hash functions shouldn't throw exceptions. It's also a
requirement for the standard library-provided hash functions to not
throw exceptions.
An exception to this rule is made for user-defined specializations,
however we can just be consistent with the standard library on this to
allow it to play nicer with it.
While we're at it, we can also make the std::less specializations
noexcpet as well, since they also can't throw.
2020-04-22 21:01:43 +01:00
Lioncash
3b46b4a37d
A64: Implement SQRDMULH's scalar vector variant
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Implements the scalar variant in terms of the vector variant for the
time being.
2020-04-22 21:01:43 +01:00
Lioncash
fe95575b95
general: Replace unreachable-imitating assertions with UNREACHABLE()
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We can just use the self-documenting assertion for indicating
unreachable paths, instead of manually passing false and providing a
message.
2020-04-22 21:01:43 +01:00
Merry
4a3d808354
Merge pull request #468 from lioncash/const
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ir_opt: Mark locals as const where applicable
2020-04-22 21:01:43 +01:00
Lioncash
64de80839e
A64/impl: Reorganize peculiar void use in V_scalar
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To a reader this might look particularly strange, given the function
itself has a void return value, but this is actually valid, given the
function in the return statement also has a void return value.
This instead alters it to be a little easier to parse and potentially be
a little less confusing at a glance.
2020-04-22 21:01:43 +01:00
Merry
9a4e3b24e4
Merge pull request #467 from lioncash/reserved
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A64: Handle reserved instruction cases more specifically where applicable
2020-04-22 21:01:43 +01:00
Merry
0b794cbcea
Merge pull request #466 from lioncash/fcmla
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A64: Implement FCMLA's indexed element variant
2020-04-22 21:01:43 +01:00
Merry
994349d154
Merge pull request #465 from neobrain/master
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CMakeLists: Allow importing dynarmic build trees into other CMake projects
2020-04-22 21:01:43 +01:00
Lioncash
cfd7513a7d
ir_opt/verification_pass: Mark locals as const where applicable
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Makes our immutable state a little more explicit.
2020-04-22 21:01:40 +01:00
Lioncash
8309d49588
A64: Handle reserved instruction cases more specifically where applicable
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These are cases that are defined as reserved within the ARMv8 reference
manual, so we can handle them as such instead of as unallocated
encodings.
While this doesn't actually change emulated behavior, it does at least
allow the JIT to generate the more appropriate exception.
2020-04-22 21:00:47 +01:00
Lioncash
6c2c68bce6
A64: Implement FCMLA's indexed element variant
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With this, all of the instructions introduced with ARMv8.3-CompNum have
an implementation.
2020-04-22 21:00:47 +01:00
Tony Wasserka
7d99a6c00f
CMakeLists: Allow importing dynarmic build trees into other CMake projects
2020-04-22 21:00:47 +01:00
Lioncash
1a45f35b9c
ir_opt/a64_callback_config_pass: Mark locals as const where applicable
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Makes our immutable state a little more explicit.
2020-04-22 21:00:47 +01:00
Lioncash
7bc7042104
simd_scalar_shift_by_immediate: Change UnallocatedEncoding() path in SaturatingShiftLeft to ReservedValue()
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Strictly speaking, immh being zero is defined as reserved in the ARMv8
reference manual. This was just an error on my part when introducing the
SQSHL immediate scalar variant.
2020-04-22 21:00:47 +01:00
Lioncash
dc97977576
ir_opt/a32_get_set_elimination_pass: Mark local variables as const where applicable
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Makes our intended immutable state slightly more explicit.
2020-04-22 21:00:47 +01:00
Lioncash
b1b4487e4d
A64: Implement UQSHL (immediate)'s scalar variant
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Like SQSHL's immediate scalar variant, we can also implement UQSHL's
immediate scalar variant in terms of the vector variant for the time
being.
2020-04-22 21:00:47 +01:00
Lioncash
3649dc6d9a
A64: Implement scalar variant of SQSHL (immediate)
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This can be handled in terms of the vector variant for the time being.
2020-04-22 21:00:47 +01:00
Lioncash
7d535eaba6
ir_opt/a32_constant_memory_reads_pass: Apply const where applicable to locals
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Makes immutable state just slightly more explicit.
2020-04-22 21:00:47 +01:00
Lioncash
e1b4ff1068
simd_scalar_shift_by_immediate: Migrate SQSHL implementation to file-scope function
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This will allow it to be reused for the implementation of UQSHL.
2020-04-22 21:00:47 +01:00
Lioncash
b37279f65c
backend/x64/emit_x64_vector: Prevent undefined behavior within VectorSignedSaturatedShiftLeft
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Avoids undefined behavior by potentially left-shifting a signed negative
value.
2020-04-22 21:00:47 +01:00
Lioncash
46eae8cf2f
common/fp/op/FPRecipExponent: Prevent undefined behavior from shifting a negative value
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Due to promotion rules (types < int, even if unsigned, get promoted to
int when arithmetic is performed on them), this is a potential spot for
undefined behavior.
2020-04-22 21:00:47 +01:00
MerryMage
13e8b7b516
emit_x64_floating_point: F16C implementation of FPSingleToHalf
2020-04-22 20:58:17 +01:00
MerryMage
d32d6fe598
emit_x64_floating_point: F16C implementation of FPHalfToSingle and FPHalfToDouble
2020-04-22 20:58:12 +01:00
MerryMage
a53ba12be2
emit_x64_floating_point: Factor out ConvertRoundingModeToX64Immediate
2020-04-22 20:58:12 +01:00
MerryMage
5a2adc6629
backend/x64: Expose FPCR in EmitContext instead of its subcomponents
2020-04-22 20:58:12 +01:00
Merry
01bb1cdd88
Merge pull request #458 from lioncash/float-op
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A64: Handle half-precision floating point in FABS, FNEG, and scalar FMOV
2020-04-22 20:58:12 +01:00
Lioncash
28a8b4d210
A64: Handle half-precision floating point in scalar FMOV
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This is simply performing a scalar value transfer between registers
without conversions, so this is trivial to handle as-is.
2020-04-22 20:58:12 +01:00
Lioncash
d7ac5a664f
A64: Handle half-precision floating point in FCVTL
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Like FCVTN, now that we have half-precision floating point conversion
functions available, we can go ahead and use those to eliminate the
interpreter fallback.
2020-04-22 20:58:12 +01:00
Lioncash
fe84ecb780
A64: Handle half-precision floating point in scalar FABS
...
Now that we have the half-precision variant of the opcode added, we can
simply handle the instruction instead of treating it as undefined.
2020-04-22 20:58:12 +01:00
Lioncash
fac9224d5e
A64: Handle half-precision floating point in FCVTN
...
Now that we have IR instructions for performing conversions with
half-precision floating point, we can also handle half-precision values
within FCVTN.
2020-04-22 20:58:12 +01:00
Lioncash
8309ec7a9f
frontend/ir_emitter: Add half-precision variant of FPAbs
2020-04-22 20:58:12 +01:00
Lioncash
16de99d3e3
A64: Enable FCVT floating-point conversions for half-precision
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With this, we no longer have to fall back to the interpreter in any of
the FCVT floating-point conversion instructions.
2020-04-22 20:58:12 +01:00
Lioncash
10abc77fad
A64: Handle half-precision floating point in scalar FNEG
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With the half-precision variant of the FPNeg opcode added, we can
utilize it here to emulate the half-precision variant of FNEG.
2020-04-22 20:58:12 +01:00
Lioncash
e4c259d69f
frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes
2020-04-22 20:58:12 +01:00
Lioncash
c97efcb978
frontend/ir_emitter: Add half-precision variant of FPNeg
2020-04-22 20:58:12 +01:00
Lioncash
dff5da1063
common/fp/unpacked: Amend behavior of FPUnpackCV
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This is supposed to call FPUnpackBase instead of FPUnpack. This would
result in alternate half-precision representations being misinterpreted
when it comes to dealing with NaNs.
2020-04-22 20:58:12 +01:00
Merry
f01afc5ae6
Merge pull request #456 from lioncash/mov
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A64: Enable FMOV (general) for half-precision floating point
2020-04-22 20:58:12 +01:00
Lioncash
03bc2334fe
common/fp/op/FPConvert: Amend off-by one in double NaN case in FPConvertNaN
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Avoids potentially clobbering the intended sign bit value during
conversions to double-precision values. The other conversion types are
already properly handled, so those don't need to be addressed.
2020-04-22 20:58:12 +01:00
Lioncash
c57b146fb2
common/fp/op/FPConvert: Add half-precision instantiations to FPConvert
2020-04-22 20:58:12 +01:00
Merry
c1ce94872d
Merge pull request #455 from lioncash/sqrdmulh-scalar
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A64: Implement SQRDMULH and SQDMULL's scalar indexed variants
2020-04-22 20:58:11 +01:00
Lioncash
25a7256ee1
A64: Enable FMOV (general) for half-precision floating point
...
This just transfers values between vector registers and general-purpose
registers with no conversions performed, so this is trivial to add
support for half-precision to.
2020-04-22 20:58:11 +01:00
Lioncash
97dd3d0596
A64: Implement SQRDMULH's scalar indexed element variant
2020-04-22 20:58:11 +01:00
Lioncash
49b51e34f1
simd_vector_x_indexed_element: Deduplicate index and Vm operand construction
2020-04-22 20:58:11 +01:00
Lioncash
692aba91b6
A64: Implement SQDMULL{2}'s scalar indexed element variant
2020-04-22 20:58:11 +01:00
Lioncash
c043b831d5
A64: Implement SQDMULL{2}'s by-element variant
2020-04-22 20:58:11 +01:00
Lioncash
72af5a3dff
simd_scalar_x_indexed_element: Factor out index and Vm argument construction
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This will be useful in the implementations of SQRDMULH and SQDMULL{2} as
well.
2020-04-22 20:58:11 +01:00
Lioncash
224ff0afaa
A64: Implement SQRDMULH's by-index vector variant
2020-04-22 20:58:11 +01:00
Lioncash
3a3542414b
A64: Implement FRECPX's half-precision floating point variant
2020-04-22 20:58:11 +01:00
Lioncash
bd892ec4ef
frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point
2020-04-22 20:58:11 +01:00
Lioncash
974fbf0677
frontend/ir/value: Add U16U32U64 type to represent floating point types
2020-04-22 20:58:11 +01:00
Lioncash
eb3e0d5908
common/fp/op/FPRecipExponent: Add half-precision floating point specialization
2020-04-22 20:58:11 +01:00
Lioncash
a829c93406
common/fp/unpacked: Correct edge-cases within FPUnpack for half-precision floating point
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This corrects one case where floating-point exceptions could be set when
they're not supposed to be.
This also corrects a case where values were being treated as NaNs when
they weren't supposed to be.
2020-04-22 20:58:11 +01:00
Lioncash
7030b9af95
common/fp/process_nan: Add half-precision instantiations for NaN processing functions
2020-04-22 20:58:11 +01:00
Lioncash
14f55d7476
common/fp/unpacked: Add half-precision instantiation of FPRoundBase
2020-04-22 20:58:11 +01:00
Lioncash
7e814de445
common/fp/unpacked: Handle half-precision unpacking in FPUnpackBase
2020-04-22 20:58:11 +01:00
Lioncash
8f9fe8690a
common/fp/unpacked: Adjust FPUnpack to operate like ARM pseudocode
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This function is defined as always disabling the AHP bit in the fpcr
before performing any operations.
At the same time, rename the original FPUnpack function to FPUnpackBase
to match the pseudocode in the ARM reference manual.
2020-04-22 20:58:11 +01:00
Merry
37c4c39d62
Merge pull request #448 from lioncash/saturate
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A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants
2020-04-22 20:58:11 +01:00
Merry
f5d774bdbd
Merge pull request #449 from lioncash/hp
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common/fp/info: Add specialization of FPInfo for half-precision floating point
2020-04-22 20:58:11 +01:00
Lioncash
126c29a9e9
A64: Implement SQSHRN, SQSHRUN, and UQSHRN's scalar variants
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These can just be implemented in terms of the vector variants for the
time being.
2020-04-22 20:58:11 +01:00
Lioncash
0b67b94b6c
common/fp/info: Add specialization of FPInfo for half-precision floating point
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Puts the necessary info struct in place for further use.
2020-04-22 20:58:11 +01:00
Lioncash
dd7433f9d3
A64: Amend prototypes of some SIMD scalar shift by immediate opcodes
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These take a vector for a destination.
2020-04-22 20:58:11 +01:00
Lioncash
99c494bae9
common/fp/unpacked: Add FPRoundCV
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Corresponds to the equivalent pseudocode within the ARMv8 reference
manual. This will be necessary for supporting half-precision
floating-point.
This also makes use of it within FPConvert
2020-04-22 20:58:11 +01:00
Merry
bbd5330ad2
Merge pull request #447 from lioncash/flag
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A64: Implement CFINV, RMIF, AXFlag and XAFlag
2020-04-22 20:58:11 +01:00
Lioncash
490bebbd9a
common/fp/unpacked: Add FPUnpackCV
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Adds a template function that performs the same behavior as in the ARM
pseudocode, and utilizes it in FPConvert, which will be necessary for
half-float support.
2020-04-22 20:58:11 +01:00
Merry
fb039e232c
Merge pull request #442 from lioncash/fcvtxn
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A64: Implement scalar and vector variants of FCVTXN
2020-04-22 20:58:11 +01:00
Lioncash
6aed4036ef
ir_opt/a64_get_set_elimination_pass: Add handling for NZCV raw get and set operations
2020-04-22 20:58:11 +01:00
Merry
4f937c1ee1
Merge pull request #446 from lioncash/sqshl
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A64: Implement scalar variants of SQSHL (register) and UQSHL (register)
2020-04-22 20:58:11 +01:00
Lioncash
aa22db534b
A64: Implement AXFlag and XAFlag
2020-04-22 20:58:11 +01:00
Merry
d74cccbc84
Merge pull request #445 from lioncash/sqrt
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A64: Implement single and double-precision vector variant of FSQRT
2020-04-22 20:58:11 +01:00
Lioncash
20ffe568d0
A64: Implement RMIF
2020-04-22 20:58:11 +01:00