Fernando Sahmkow
97b9d3e058
Exclusive Monitor: Rework exclusive monitor interface.
2020-05-03 01:40:37 +01:00
MerryMage
5c0bb5cc63
Remove unreachable code (MSVC warnings)
2020-04-23 16:36:34 +01:00
MerryMage
a8a712c801
Relicense to 0BSD
2020-04-23 15:45:57 +01:00
Lioncash
43fd2b400a
frontend/ir_emitter: Add half-precision opcode for FPVectorEquals
2020-04-22 21:04:22 +01:00
Lioncash
bd755ae494
frontend/ir/ir_emitter: Add A32 equivalent to A64's SetCheckBit
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This will be used in a subsequent change to implement ARMv6T2's CBZ/CBNZ
Thumb-1 instructions.
2020-04-22 21:02:47 +01:00
Lioncash
8316d231e9
A32: Implement barrier instructions introduced in ARMv7
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Provides basic implementations of the barrier instruction introduced
within ARMv7. Currently these simply mirror the behavior of the AArch64
equivalents.
2020-04-22 21:02:46 +01:00
Merry
09ee64ea98
Merge pull request #482 from lioncash/fixedfp
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A64: Handle half-precision variants of FP->Fixed instructions
2020-04-22 21:02:45 +01:00
Lioncash
427b7afd66
frontend/ir/microinstruction: Add missing fixed-point opcodes to ReadsFromAndWritesToFPSRCumulativeExceptionBits()
2020-04-22 21:01:45 +01:00
Lioncash
604f39f00a
frontend/ir_emitter: Add half-precision->fixed-point opcodes
2020-04-22 21:01:45 +01:00
Lioncash
96356fac93
frontend/ir_emitter: Add half-precision opcode variant of FPVectorRSqrtStepFused
2020-04-22 21:01:45 +01:00
Merry
45864133f5
Merge pull request #478 from lioncash/stepfused
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A64: Handle half-precision variants of FRECPE and FRECPS
2020-04-22 21:01:44 +01:00
Lioncash
824c551ba2
frontend/ir_emitter: Add half-precision opcode variant of FPRSqrtStepFused
2020-04-22 21:01:44 +01:00
Lioncash
037acb17b9
frontend/ir_emitter: Add half-precision opcode variant for FPVectorRSqrtEstimate
2020-04-22 21:01:44 +01:00
Lioncash
5dba99b4f4
frontend/ir_emitter: Add half-precision opcode variant for FPRSqrtEstimate
2020-04-22 21:01:44 +01:00
Lioncash
825a3ea16f
frontend/ir_emitter: Add half-precision opcode for FPVectorRecipEstimate
2020-04-22 21:01:44 +01:00
Lioncash
2184d24e8f
frontend/ir_emitter: Add half-precision opcode for FPRecipEstimate
2020-04-22 21:01:44 +01:00
Lioncash
5d5c9f149f
frontend/ir_emitter: Add half-precision opcode for FPVectorRecipStepFused
2020-04-22 21:01:44 +01:00
Lioncash
6da0411111
frontend/ir_emitter: Add half-precision opcode for FPRecipStepFused
2020-04-22 21:01:44 +01:00
Lioncash
fb829b9525
frontend/microinstruction: Add FPVectorRoundInt types to ReadsFromAndWritesToFPSRCumulativeExceptionBits()
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All variants were previously missing from this.
2020-04-22 21:01:44 +01:00
Lioncash
ad0c698f89
frontend/ir_emitter: Add half-precision variant of FPRoundInt
2020-04-22 21:01:44 +01:00
Merry
cb9a1b18b6
Merge pull request #475 from lioncash/muladd
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A64: Enable half-precision variants of floating-point multiply-add instructions
2020-04-22 21:01:44 +01:00
Lioncash
a4cadf1cd9
frontend/ir_emitter: Add opcodes for signed saturated left shifts with unsigned saturation
2020-04-22 21:01:44 +01:00
Lioncash
ec6b3ae084
ir/frontend: Add half-precision opcode for FPVectorMulAdd
2020-04-22 21:01:44 +01:00
Lioncash
bd82513199
frontend/ir_emitter: Add half-precision opcode for FPMulAdd
2020-04-22 21:01:44 +01:00
Lioncash
e4c259d69f
frontend/ir_emitter: Add half->{single, double} and {double, single}->half conversion opcodes
2020-04-22 20:58:12 +01:00
Lioncash
bd892ec4ef
frontend/ir/ir_emitter: Amend FPRecipExponent to handle half-precision floating point
2020-04-22 20:58:11 +01:00
Lioncash
597a8be5d5
ir: Add A64-specific opcodes for getting and setting raw NZCV values
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This will be necessary to implement the flag manipulation and flag
format instructions.
2020-04-22 20:58:11 +01:00
Lioncash
5cf1478620
frontend/ir: Add opcodes for vector square roots
2020-04-22 20:58:10 +01:00
Lioncash
36027ebef5
frontend/ir/microinstruction: Add missing cases for FPRecipExponent{32,64} for ReadsFromAndWritesToFPSRCumulativeExceptionBits()
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This was intended to be added within #437 , but was missed
2020-04-22 20:58:10 +01:00
Lioncash
d426dfe942
ir: Add opcodes for unsigned saturating left shifts
2020-04-22 20:55:06 +01:00
MerryMage
02150bc0b7
IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed
2020-04-22 20:55:06 +01:00
MerryMage
90193b0e3d
IR: Add fbits argument to FixedToFP-related opcodes
2020-04-22 20:55:06 +01:00
Lioncash
b14eaaec46
ir: Add opcodes for left signed saturated shifts
2020-04-22 20:55:06 +01:00
MerryMage
3e447614c6
IR: Add VectorSignedSaturatedDoublingMultiplyLong
2020-04-22 20:55:06 +01:00
MerryMage
06b31448aa
emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply
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* Return both the upper and lower parts of the multiply if required
* SSE2 does not support the pmuldq instruction, do sign correction to an unsigned result instead
* Improve port utilisation where possible (punpck instructions were a bottleneck)
2020-04-22 20:55:06 +01:00
MerryMage
08c0e017a5
IR: Implement Vector{Signed,Unsigned}Multiply{16,32}
2020-04-22 20:55:06 +01:00
Lioncash
d4a76aaa04
ir: Add opcodes form unsigned saturated accumulations of signed values
2020-04-22 20:55:05 +01:00
Lioncash
6f911a26da
ir: Add opcodes for signed saturated accumulations of unsigned values
2020-04-22 20:55:05 +01:00
Lioncash
fca7eddb9e
A64: Add opcodes for signed saturating negations
2020-04-22 20:53:46 +01:00
Lioncash
a0231e5546
ir: Add opcodes for signed saturated doubling multiplies
2020-04-22 20:53:46 +01:00
Lioncash
0507e47420
ir: Add opcodes for signed saturated absolute values
2020-04-22 20:53:46 +01:00
MerryMage
ccbf6c7f63
microinstruction: A32ExceptionRaised causes CPU exception
2020-04-22 20:53:46 +01:00
MerryMage
89d08c7d61
IR: Add VectorTable and VectorTableLookup IR instructions
2020-04-22 20:53:45 +01:00
Lioncash
f3f60cd179
A64: Implement ISB
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Given we want to ensure that all instructions are fetched again, we can
treat an ISB instruction as a code cache flush.
2020-04-22 20:53:45 +01:00
MerryMage
3f4d118d73
microinstruction: Improve assert messages
2020-04-22 20:46:23 +01:00
MerryMage
ddcff86f9c
microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
2020-04-22 20:46:22 +01:00
MerryMage
ecbf9dbae5
IR: Implement A64OrQC
2020-04-22 20:46:22 +01:00
MerryMage
b455b566e7
A64: Implement UQXTN (vector)
2020-04-22 20:46:22 +01:00
MerryMage
3874cb37e3
A64: Implement SQXTN (vector)
2020-04-22 20:46:22 +01:00
MerryMage
f020dbe4ed
A64: Implement SQXTUN
2020-04-22 20:46:22 +01:00
