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700088408d emit_x64_floating_point: Simplify EmitFP{Min,Max}{,Numeric}{32,64} MerryMage 2018-08-02 20:16:03 +0100
07e0585994 emit_x64_floating_point: Reduce NaN processing overhead MerryMage 2018-08-02 17:17:23 +0100
f5e11d117a A64: Implement FMULX, scalar single/double variant MerryMage 2018-08-02 14:11:30 +0100
17f73974f2 IR: Implement FPMulX IR instruction MerryMage 2018-08-02 14:11:14 +0100
a8b938ef32 fuzz_with_unicorn: Randomize SP MerryMage 2018-08-01 15:30:43 +0100
9a7d75be3b fuzz_with_unicorn: Randomize PC MerryMage 2018-08-01 15:26:03 +0100
ff84740ea6 testenv: Make code_mem mobile MerryMage 2018-08-01 15:25:40 +0100
391e16be64 emit_x64_vector: Vectorize 32-bit variants of paired min/max Lioncash 2018-07-31 16:20:19 -0400
5ae045d67e emit_x64_vector: Improve code emission of VectorGetElement* for index == 0 MerryMage 2018-07-31 22:04:11 +0100
e9ab7f7664 reg_alloc: Do a UseScratch if a Use destination is too small MerryMage 2018-07-31 21:55:14 +0100
63eb4e0f31 fuzz_with_unicorn: Randomize FPCR.AHP and FPCR.FZ16 MerryMage 2018-07-31 21:27:24 +0100
90f8dda966 emit_x64_floating_point: AVX implementation of ForceToDefaultNaN MerryMage 2018-07-31 21:22:01 +0100
dfb660cd16 emit_x64_vector_floating_point: Prefer blendvp{s,d} to vblendvp{s,d} where possible MerryMage 2018-07-31 21:03:48 +0100
476c0f15da backend_x64: Remove all use of xmm0 MerryMage 2018-07-31 20:53:33 +0100
8252efd7b1 emit_x64_vector_floating_point: AVX implementation of ForceToDefaultNaN MerryMage 2018-07-31 20:33:50 +0100
746dc521b9 emit_x64_vector_floating_point: Reduce codesize of ForceToDefaultNaN MerryMage 2018-07-31 20:25:56 +0100
7731dcdca9 emit_x64_vector_floating_point: Reduce codesize of EmitTwoOpVectorOperation MerryMage 2018-07-31 20:25:03 +0100
bb93353f94 emit_x64_vector_floating_point: Correct FMA in FTZ mode MerryMage 2018-07-31 18:12:39 +0100
8ef195db3c emit_x64_floating_point: DenormalsAreZero is redundant as hardware already does DAZ MerryMage 2018-07-31 18:03:59 +0100
de9d8c461c emit_x64_floating_point: FlushToZero is redundant as hardware already does FTZ MerryMage 2018-07-31 16:08:13 +0100
822fd4a875 backend_x64: Fix FPVectorMulAdd and FPMulAdd NaN handling with denormals MerryMage 2018-07-31 16:07:46 +0100
381821eda3 a32/fuzz_arm: Disable vfp tests MerryMage 2018-07-31 16:01:28 +0100
868ec44f30 fuzz_with_unicorn: Randomize FPCR.FZ MerryMage 2018-07-31 15:35:30 +0100
b393e15ab6 backend_x64: Fix bugs when FPCR.FZ=1 MerryMage 2018-07-31 15:32:14 +0100
2b538b471f fuzz_with_unicorn: Extract RandomFpcr function MerryMage 2018-07-31 12:35:04 +0100
5e88d66470 fp/info: Deduplicate functions MerryMage 2018-07-30 20:25:29 +0100
2019d32743 emit_x64_floating_point: Deduplicate EmitFPMulAdd implementation MerryMage 2018-07-30 20:16:45 +0100
e038fe72df emit_x64_floating_point: Deduplicate code MerryMage 2018-07-30 15:13:43 +0100
f2344f4c87 fuzz_with_unicorn: Randomize FPCR.DN MerryMage 2018-07-30 14:36:22 +0100
ec82a845b7 emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1 MerryMage 2018-07-30 14:35:48 +0100
7f27945411 emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1 MerryMage 2018-07-30 14:35:29 +0100
21a28c2545 IR: SSE4.1 implementation of FPVectorRoundInt MerryMage 2018-07-30 13:48:04 +0100
9669e49817 A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant MerryMage 2018-07-30 13:32:20 +0100
f976c47008 IR: Initial implementation of FPVectorRoundInt MerryMage 2018-07-30 13:31:51 +0100
f2393488fe A64: Implement SQADD and SQSUB, scalar variant MerryMage 2018-07-30 11:00:20 +0100
10e196480f IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths MerryMage 2018-07-30 10:59:52 +0100
71db0e67ae a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument MerryMage 2018-07-30 10:59:18 +0100
d0fdd3c6e6 simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function Lioncash 2018-07-29 17:43:10 -0400
2bea2d0512 A64: Implement SMAXP, SMINP, UMAXP, UMINP Lioncash 2018-07-29 17:35:11 -0400
463b9a3d02 ir: Add opcodes for vector paired maximum and minimums Lioncash 2018-07-29 16:08:31 -0400
43344c5400 A64: Implement SMAXV, SMINV, UMAXV, and UMINV Lioncash 2018-07-29 19:00:18 -0400
2501bfbfae ir: Add opcodes for performing scalar integral min/max Lioncash 2018-07-29 17:52:27 -0400
7fdd8b0197 A64: Implement PMULL{2} Lioncash 2018-07-26 12:24:47 -0400
5ebf496d4e translate: Deduplicate GetDataSize() functions Lioncash 2018-07-29 00:53:13 -0400
f83cd2da9a floating_point_{conditional}_compare: Deduplicate code Lioncash 2018-07-29 00:45:26 -0400
f9c6d5e1a0 common: Move all cryptographic function to common/crypto MerryMage 2018-07-29 08:48:28 +0100
5dc23e49d7 a32_emit_x64: BMI2 implementation of A32SetCpsr MerryMage 2018-07-27 11:41:31 +0100
0f85305933 a32_emit_x64: Shorten EmitA32GetCpsr MerryMage 2018-07-27 11:15:52 +0100
9fe2bf8733 a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid MerryMage 2018-07-26 19:25:35 +0100
b48fb8ca6b A64: Implement PMUL Lioncash 2018-07-26 04:21:50 -0400
affa312d1d ir: Add opcode for performing polynomial multiplication Lioncash 2018-07-26 03:40:09 -0400
dd4ac86f8e A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant MerryMage 2018-07-26 12:46:12 +0100
28b38916a8 A64: Implement FCVTZS (vector, integer), single/double variant MerryMage 2018-07-26 12:10:00 +0100
507bcd8b8b IR: Implement FPVectorTo{Signed,Unsigned}Fixed MerryMage 2018-07-26 12:08:56 +0100
8f75a1fe04 fp/info: Replace constant value generators with FPValue MerryMage 2018-07-26 10:59:33 +0100
da261772ea emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min} MerryMage 2018-07-26 10:10:47 +0100
a0d6f0de57 emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs MerryMage 2018-07-26 09:42:34 +0100
c778c7b868 A64: Implement FMAX's vector single and double precision variants Lioncash 2018-07-07 15:38:18 -0400
009879d92b A64: Implement FMIN's vector single and double precision variants Lioncash 2018-07-07 15:29:53 -0400
7b03da86c2 IR: Implement FPVector{Max,Min} MerryMage 2018-07-07 15:20:00 -0400
e76e1186bb FPRecipEstimate: Move offset out of function MerryMage 2018-07-25 19:22:16 +0100
ddcff86f9c microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits MerryMage 2018-07-25 19:17:07 +0100
10de36394e A64: Implement FRECPS, vector/scalar single/double variants MerryMage 2018-07-25 19:11:43 +0100
901bd9b4e2 IR: Implement FPRecipStepFused, FPVectorRecipStepFused MerryMage 2018-07-25 19:11:20 +0100
f66f61d8ab A64: Implement FRECPE, vector single/double variant MerryMage 2018-07-25 18:55:58 +0100
939f5f5c7a IR: Implement FPVectorRecipEstimate MerryMage 2018-07-25 18:55:40 +0100
27c73dd56a A64: Implement FRECPE, scalar single/double variant MerryMage 2018-07-25 18:47:45 +0100
fc2d33ae7b IR: Implement FPRecipEstimate MerryMage 2018-07-25 18:44:19 +0100
c1dcfe29f7 IR: Implement FPRecipEstimate MerryMage 2018-07-25 18:36:40 +0100
7a673a8a43 fp: Change FPUnpacked to a normalized representation MerryMage 2018-07-25 17:39:14 +0100
680395a803 fuzz_with_unicorn: Disable testing of FDIV MerryMage 2018-07-25 14:05:13 +0100
3fe45c6d8e block_of_code: Add ABI_PARAMS array MerryMage 2018-07-25 13:58:54 +0100
642b6c31d2 A64: Implement MLA, MLS (by element), vector single/double variant MerryMage 2018-07-25 13:54:48 +0100
0de37b11ad A64: Implement FMLS (vector), single/double variant MerryMage 2018-07-25 13:45:02 +0100
64c2f698a2 emit_x64_vector_floating_point: Specify NanHandler::function_type explicitly MerryMage 2018-07-25 13:37:11 +0100
2ef59b4f03 emit_x64_vector_floating_point: ChooseOnFsize arguments maybe_unused MerryMage 2018-07-25 13:27:31 +0100
04f325a05e IR: Implement FPVectorNeg MerryMage 2018-07-25 13:25:35 +0100
934132e0c5 A64: Implement FMLA (vector), single/double variant MerryMage 2018-07-25 13:20:07 +0100
771a4fc20b IR: Implement FPVectorMulAdd MerryMage 2018-07-25 13:19:48 +0100
3218bb9890 emit_x64_vector_floating_point: Standardize naming scheme MerryMage 2018-07-25 12:08:00 +0100
8f72be0a02 emit_x64_floating_point: Simplify indexers MerryMage 2018-07-25 12:05:41 +0100
25b28bb234 emit_x64_vector_floating_point: Simplify EmitVectorOperation* MerryMage 2018-07-25 11:29:50 +0100
1edd0125b2 mp: rename mp.h to mp/function_info.h MerryMage 2018-07-25 11:28:36 +0100
0921678edb emit_x64_vector: Slightly improve ArithmeticShiftRightByte MerryMage 2018-07-25 09:33:02 +0100
43407c4bb4 emit_x64_vector: Simplify VectorShuffleImpl MerryMage 2018-07-24 22:44:55 +0100
ecbf9dbae5 IR: Implement A64OrQC MerryMage 2018-07-24 19:04:40 +0100
f0fecf2615 A64: Implement UQSHRN, UQRSHRN (vector) MerryMage 2018-07-24 18:54:28 +0100
8f4c1a8558 emit_x64_vector: -0x80000000 isn't -0x80000000 MerryMage 2018-07-24 18:45:45 +0100
b455b566e7 A64: Implement UQXTN (vector) MerryMage 2018-07-24 18:17:45 +0100
e686a81612 emit_x64_vector: Fix non-SSE4.1 saturated narrowing reconstruction comparison MerryMage 2018-07-24 18:17:14 +0100
3874cb37e3 A64: Implement SQXTN (vector) MerryMage 2018-07-24 17:59:14 +0100
8ef114d48f emit_x64_vector: packusdw reqiures SSE4.1 MerryMage 2018-07-24 17:32:00 +0100
712c6c1d7e A64: Implement SQSHRUN, SQRSHRUN (vector) MerryMage 2018-07-24 17:20:49 +0100
c5722ec963 simd_shift_by_immediate: Simplify ShiftRight MerryMage 2018-07-24 16:38:51 +0100
f020dbe4ed A64: Implement SQXTUN MerryMage 2018-07-24 16:06:55 +0100
6918ef7360 microinstruction: Reorganize FPSCR related instruction queries MerryMage 2018-07-24 12:10:57 +0100
a639fa5534 microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() Lioncash 2018-07-22 22:49:35 -0400
3ca18d8a6d u128: Make Bit() a const-qualified member function Lioncash 2018-07-23 17:52:52 -0400
b2e4c16ef8 A64: Implement FRSQRTS (vector), single/double variant MerryMage 2018-07-23 22:58:52 +0100
45dc5f74f3 A64: Implement FRSQRTE (vector), single/double variant MerryMage 2018-07-23 22:46:12 +0100