MerryMage
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47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f3fa4a042f
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a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8698f057d0
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a6cc667509
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f45a5e17c6
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Implement direct page table access
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bfd3e30c75
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callbacks: Member functions should be const
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9f2f08db8d
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c4773e85b
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8756487554
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A64: Partially implement MRS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bfd65bedfe
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A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5edd623b9d
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2cb0a699ba
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IR: Implement FPMax, FPMin
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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98c8e7d1af
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IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eae518a338
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IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b9cd345ddc
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IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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851fc83445
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emit_x64_vector: EmitOneArgumentFallback
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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303088a51e
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IR: Implement VectorPopulationCount
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bf2cd92da9
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emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b062266b8e
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emit_x64_vector: More explicit lambda decay
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b6de612e01
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IR: Implement VectorMultiply
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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90a053a5e4
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emit_x64_vector: Order alphabetically
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1423584f9f
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constant_pool: Allow for 128-bit constants
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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69de50a878
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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f6247125c0
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IR: Implement VectorLogicalShiftLeft{8,16,32,64}
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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15e8231f24
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opcodes: Sort vector IR opcodes alphabetically
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d74f4e35f6
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block_of_code: Increase constant pool size
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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e69288f803
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devirtualize: MinGW uses Intanium MFP ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ad428cbd7a
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callback: Properly handle calls with return pointers and simplify interface
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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7a87e3fc55
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devirtualize: Handle Windows ABI
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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f808a0fbde
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devirtualize: Devirtualize Itanium ABI MFPs at runtime
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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35a29a9665
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A64: Implement ZIP1
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2020-04-22 20:46:13 +01:00 |
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FernandoS27
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586854117b
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Implemented UMULH and SMULH instructions
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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44c3c2312a
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a64_jitstate: Remove unnecessary FPSCR_nzcv member
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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aac5af50e2
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IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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dd2a6684fe
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IR: Add ConditionalSelectNZCV instruction
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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b173fcf34e
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backend_x64: Simplify FPDoubleToU32 and FPSingleToU32
They're inaccurate in terms of FPSR at the moment anyway.
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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d040920727
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Common: Put AES code within its own nested namespace
Prevents the functions from potentially clashing with other stuff in Common in the future
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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40614202e7
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A64: Implement AESD
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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ccef85dbb7
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A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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68f46c8334
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backend_x64: Use a reference to BlockOfCode instead of a pointer
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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8931ee346b
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IR: Add IR instruction NZCVFromPackedFlags
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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75b8a76630
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a64_jitstate: A64 does not have a seperate FPSCR.NZCV
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2020-04-22 20:46:13 +01:00 |
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