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339 commits

Author SHA1 Message Date
MerryMage
55eaa16615 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT 
Discovered by @Subv.
Fixes incomplete fix begun in 5a91c94dca47c9702dee20fbd5ae1f4c07eef9df.
That fix fails to take into account that LinkBlock doesn't update ticks until there
are no remaining ticks to be executed.

Test added to confirm fix.
 2020-04-22 20:46:21 +01:00
Lioncash
e5d80e998e A64: Implement SADDLV 2020-04-22 20:46:21 +01:00
Lioncash
a1bc8ddb53 A64: Implement UADDLV 2020-04-22 20:46:21 +01:00
MerryMage
b53127600b fp: A64::FPCR -> FP::FPCR 2020-04-22 20:46:21 +01:00
MerryMage
699c5f36d5 system: Simplify static_cast 2020-04-22 20:46:21 +01:00
MerryMage
3f602129f4 system: Ensure value of CNTPCT_EL0 is accurate 
Since we currently only update the host's tick count at the end of a
block, we force an end-of-block before executing a MRS %, CNTPCT_ELO
instruction.
 2020-04-22 20:46:21 +01:00
Lioncash
af3e23b224 simd_scalar_shift_by_immediate: Implement FCVT{ZS, ZU} (vector, fixed-point)'s scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
Lioncash
91abf87169 simd_scalar_two_register_misc: Implement FCVT{AS, AU, MS, MU, NS, NU, PS, PU, ZS, ZU} (vector)'s scalar double/single-precision variants 
We can simply implement this in terms of the fixed-point IR opcodes.
 2020-04-22 20:46:21 +01:00
MerryMage
e18fca17dc A64: Implement FABD in terms of existing IR instructions 
Fixes NaN issue. Closes #306.
 2020-04-22 20:46:21 +01:00
MerryMage
a40127a054 A64: Implement FRINTX, FRINTI (scalar) 2020-04-22 20:46:20 +01:00
MerryMage
962fa3b65e A64: Implement FRINTP, FRINTM, FRINTZ (scalar) 2020-04-22 20:46:20 +01:00
MerryMage
5200bf41cf A64: Implement FRINTN (scalar) 2020-04-22 20:46:20 +01:00
MerryMage
8718dc1692 A64: Implement FRINTA (scalar) 2020-04-22 20:46:20 +01:00
Lioncash
f7f83b76b7 simd_scalar_two_register_misc: Implement scalar double/single-precision variants of FCM{EQ, GE, GT, LE, LT} (zero) 2020-04-22 20:46:20 +01:00
MerryMage
89e43867c1 A64: Implement FADDP (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
33fa65de23 A64: Implement FADDP (vector) 2020-04-22 20:46:19 +01:00
MerryMage
9dba273a8c A64: Implement SADDLP 2020-04-22 20:46:19 +01:00
MerryMage
70ff2d73b5 A64: Implement UADDLP 2020-04-22 20:46:19 +01:00
MerryMage
5563bbbd79 A64: Implement EXT 2020-04-22 20:46:19 +01:00
MerryMage
3d9677d094 A64: Implement FCVTMU (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
79c9018d60 A64: Implement FCVTMS (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
49c4499a87 A64: Implement FCVTPU (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
af661ef5a6 A64: Implement FCVTPS (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
27319822bb A64: Implement FCVTAU (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
c0c7a26314 A64: Implement FCVTAS (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
a1965a74a0 A64: Implement FCVTNU (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
7d36dbcdfd A64: Implement FCVTNS (scalar) 2020-04-22 20:46:19 +01:00
MerryMage
617ca0adf0 floating_point_conversion_integer: Refactor implementation of FCVTZS_float_int and FCVTZU_float_int 2020-04-22 20:46:19 +01:00
MerryMage
caaf36dfd6 IR: Initial implementation of FP{Double,Single}ToFixed{S,U}{32,64} 
This implementation just falls-back to the software floating point implementation.
 2020-04-22 20:46:19 +01:00
MerryMage
55d590c01f FPCR: Add AHP setter and FZ16 getter 2020-04-22 20:46:19 +01:00
Lioncash
e7409fdfe4 A64: Implement UCVTF (vector, integer)'s double/single-precision variant 2020-04-22 20:46:19 +01:00
Lioncash
fcae4e2418 simd_three_different: Deduplicate common implementations 
Generally, the only difference between the signed variants and the
unsigned variants is whether or not we use a sign-extension or
zero-extension, so we can simply use common functions to implement both
cases without totally duplicating code twice here.
 2020-04-22 20:46:19 +01:00
Lioncash
9c0d5cf15c floating_point_conversion_integer: Handle S64/U64 -> F32 conversions in SCVTF_float_int and UCVTF_float_int 2020-04-22 20:46:19 +01:00
Lioncash
a1d6a86e8c A64: Implement ADDV 2020-04-22 20:46:19 +01:00
Lioncash
245c903129 simd_three_same: Join FPAbsoluteComparison() into FPCompareRegister() 
These are part of the same comparison family, so there's no real point
in keeping them separate.
 2020-04-22 20:46:19 +01:00
Lioncash
9912836b59 A64: Implement scalar double/single-precision variants of FACGE, FACGT, FCMEQ, FCMGE, FCMGT 2020-04-22 20:46:18 +01:00
MerryMage
d875c08ebf fp: Extract common RoundingMode enum 2020-04-22 20:46:18 +01:00
Lioncash
3714bc0ed4 floating_point_conversion_integer: Use FPS64ToDouble and FPU64ToDouble in SCVTF_float_int and UCVTF_float_int 
The opcodes introduced in 979b6f39f1621b80bd463645ec5b08661cb6b1bf can
also be used here, avoiding more falling back to the interpreter.
 2020-04-22 20:46:18 +01:00
Lioncash
b97358075e simd_scalar_two_register_misc: Handle 64-bit case in SCVTF and UCVTF's scalar double/single-precision variant 
Avoids falling back to the interpreter in the 64-bit case.
 2020-04-22 20:46:18 +01:00
Lioncash
0f4bf26e05 simd_two_register_misc: Utilize FPVectorAbs in FABS implementations 
Since we already have opcodes introduced to implement FACGE and FACGT,
we can reutilize it for the FABS implementations.
 2020-04-22 20:46:18 +01:00
Lioncash
53dbb6a92a A64: Implement FACGE's vector single/double precision variants 2020-04-22 20:46:18 +01:00
Lioncash
6912a02d9b A64: Implement FACGT's vector single/double precision variants 2020-04-22 20:46:18 +01:00
Lioncash
593eca7fb1 A64: Implement load/store single structure instructions 
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
 2020-04-22 20:46:18 +01:00
Lioncash
9e75d08860 A64: Implement FABD's scalar single/double precision variant 2020-04-22 20:46:18 +01:00
Lioncash
d898d1779d A64: Implement FABD's vector single/double precision variant 2020-04-22 20:46:18 +01:00
MerryMage
ba84e7a8de A64: Implement FNMSUB 2020-04-22 20:46:18 +01:00
MerryMage
a1042cfcd8 A64: Implement FNMADD 2020-04-22 20:46:18 +01:00
MerryMage
0d83032a6f A64: Implement FMSUB 2020-04-22 20:46:18 +01:00
MerryMage
69e00d225c A64: Implement FMADD 2020-04-22 20:46:18 +01:00
Lioncash
24e3299276 A64: Implement FCMGT, FCMGE (register) vector double and single precision variants 2020-04-22 20:46:18 +01:00