MerryMage
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e3da92024e
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A64: Implement system registers FPCR and FPSR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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9e4e4e9c1d
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A64: Implement system register CNTPCT_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1e15283d00
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A64: Implement system register CTR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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58fbb3ff1b
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A64: Implement NEG (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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710d09471b
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IR: Add IR instruction ZeroVector
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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2721bb5ace
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emit_x64_floating_point: Add maybe_unused to preprocess parameter
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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0575e7421b
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1c9804ea07
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A64: Implement FMAXNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1dfce0894d
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constant_pool: Add frame parameter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bd2b415850
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A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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84f1c9b7f4
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reg_alloc: Only exchange GPRs
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9df3793af0
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A64: Implement DUP (element), scalar variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6541ec064d
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emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2080a51f41
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A64: Implement FMAX (scalar), FMIN (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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44a5b57f2a
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fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eaa1fd36a7
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travis: Switch unicorn repository
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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7c193485e1
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a64/config: Allow NaN emulation accuracy to be set
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a3df46a75a
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a64_emit_x64: Add conf to A64EmitContext
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1311f67b4a
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fuzz_with_unicorn: Explicitly test floating point instructions
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0e157b0198
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A64: Implement FSQRT (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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07520f32c3
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backend_x64: Accurately handle NaNs
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e97581d063
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fuzz_with_unicorn: Print AArch64 disassembly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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01c1e9017e
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T32: Add initial decoder list
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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ccf7df057b
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simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8cebb87d0d
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A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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7f68d556ab
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decoder/a64: Rearrange SIMD two-register misc decoders
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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d5af052f06
|
A64: Implement CMGE (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9d85991906
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A64: Implement CMHI, CMHS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e2b9b7c5b0
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IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0df6725f73
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A64: Implement SMAX, SMIN, UMAX, UMIN
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
adb7f5f86f
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A64: Implement CMGT (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f3fa4a042f
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a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9f04f2c892
|
Merge branch 'feature/exclusive-mem'
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f6a2104ab3
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fuzz_with_unicorn: Speed up tests by not initializing/tearing down constantly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8698f057d0
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a38f35eef6
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Merge branch 'feature/direct-page-table-access'
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2a6619d59c
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A64: Implement CLREX
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9f2f08db8d
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a6cc667509
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c4773e85b
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f45a5e17c6
|
Implement direct page table access
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8756487554
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A64: Partially implement MRS
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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ef02658049
|
fuzz_with_unicorn: Fix read-past-end access via jit_iter
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd65bedfe
|
A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd3e30c75
|
callbacks: Member functions should be const
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
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