MerryMage
|
d5af052f06
|
A64: Implement CMGE (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9d85991906
|
A64: Implement CMHI, CMHS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e2b9b7c5b0
|
IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
0df6725f73
|
A64: Implement SMAX, SMIN, UMAX, UMIN
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
47c0ad0fc8
|
IR: Implement Vector{Max,Min}{Signed,Unsigned}
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
adb7f5f86f
|
A64: Implement CMGT (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f4775910f5
|
IR: Implement VectorGreaterSigned
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1f5b3bca43
|
Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f3fa4a042f
|
a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9f04f2c892
|
Merge branch 'feature/exclusive-mem'
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f6a2104ab3
|
fuzz_with_unicorn: Speed up tests by not initializing/tearing down constantly
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8698f057d0
|
A64: Implement STXP, STLXP, LDXP, LDAXP
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a38f35eef6
|
Merge branch 'feature/direct-page-table-access'
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2a6619d59c
|
A64: Implement CLREX
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9f2f08db8d
|
a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a6cc667509
|
Direct Page Table Access: Handle address spaces less than the full 64-bit in size
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b7a2c1a7df
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c4773e85b
|
abi: Add RAX to ABI_ALL_CALLER_SAVE
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f45a5e17c6
|
Implement direct page table access
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8756487554
|
A64: Partially implement MRS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ef02658049
|
fuzz_with_unicorn: Fix read-past-end access via jit_iter
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd65bedfe
|
A64: Implement DSB, DMB
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd3e30c75
|
callbacks: Member functions should be const
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5edd623b9d
|
Implement DC instructions
|
2020-04-22 20:46:14 +01:00 |
|
Lioncash
|
a9153218bd
|
A64: Implement NOT (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2cb0a699ba
|
IR: Implement FPMax, FPMin
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
aed4fd3ec3
|
A64: Implement FADD (vector), vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
98c8e7d1af
|
IR: Implement FPVectorAdd
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5f77ab28ee
|
A64: Implement SSHLL, SSHLL2
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
eae518a338
|
IR: Implement VectorSignExtend
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a90e4955ab
|
CMakeLists: Ignore warnings within xbyak
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3738043e58
|
A64: Implement DUP (element), vector variant
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ce7628b6b5
|
load_store_multiple_structures: Improve IR codegen for selem == 1 case
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f1cb5581c9
|
A64: Implement FSUB (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
851fc83445
|
emit_x64_vector: EmitOneArgumentFallback
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f378d2ef1b
|
Forward declare IR::Opcode and IR::Type where possible
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c9b4f0114
|
A64: Implement CNT
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
303088a51e
|
IR: Implement VectorPopulationCount
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1dd2b33b87
|
A64: Implement MLS (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5eac3abf52
|
A64: Implement MLA (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bf2cd92da9
|
emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b062266b8e
|
emit_x64_vector: More explicit lambda decay
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3afd2fcbad
|
A64: Implement MUL (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b6de612e01
|
IR: Implement VectorMultiply
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
90a053a5e4
|
emit_x64_vector: Order alphabetically
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e7041d7196
|
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a455ff70c9
|
decoder/a64: Don't rearrange unrelated decoders
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
faeb77e8c4
|
A64: Implement SUB (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bd106c3ae7
|
A64: Implement SIMD instruction SSRA, vector variant
|
2020-04-22 20:46:14 +01:00 |
|