MerryMage
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8cebb87d0d
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A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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7f68d556ab
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decoder/a64: Rearrange SIMD two-register misc decoders
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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d5af052f06
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A64: Implement CMGE (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9d85991906
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A64: Implement CMHI, CMHS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e2b9b7c5b0
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IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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0df6725f73
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A64: Implement SMAX, SMIN, UMAX, UMIN
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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adb7f5f86f
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A64: Implement CMGT (register)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f3fa4a042f
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a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9f04f2c892
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Merge branch 'feature/exclusive-mem'
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f6a2104ab3
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fuzz_with_unicorn: Speed up tests by not initializing/tearing down constantly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8698f057d0
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a38f35eef6
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Merge branch 'feature/direct-page-table-access'
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
2a6619d59c
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A64: Implement CLREX
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
9f2f08db8d
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a6cc667509
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
b7a2c1a7df
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c4773e85b
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
f45a5e17c6
|
Implement direct page table access
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
8756487554
|
A64: Partially implement MRS
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ef02658049
|
fuzz_with_unicorn: Fix read-past-end access via jit_iter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
bfd65bedfe
|
A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd3e30c75
|
callbacks: Member functions should be const
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
5edd623b9d
|
Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
|
Lioncash
|
a9153218bd
|
A64: Implement NOT (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2cb0a699ba
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IR: Implement FPMax, FPMin
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
aed4fd3ec3
|
A64: Implement FADD (vector), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
98c8e7d1af
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IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
5f77ab28ee
|
A64: Implement SSHLL, SSHLL2
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
eae518a338
|
IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
a90e4955ab
|
CMakeLists: Ignore warnings within xbyak
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
3738043e58
|
A64: Implement DUP (element), vector variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
ce7628b6b5
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load_store_multiple_structures: Improve IR codegen for selem == 1 case
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f1cb5581c9
|
A64: Implement FSUB (vector)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
b9cd345ddc
|
IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
851fc83445
|
emit_x64_vector: EmitOneArgumentFallback
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f378d2ef1b
|
Forward declare IR::Opcode and IR::Type where possible
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c9b4f0114
|
A64: Implement CNT
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
303088a51e
|
IR: Implement VectorPopulationCount
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1dd2b33b87
|
A64: Implement MLS (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
5eac3abf52
|
A64: Implement MLA (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bf2cd92da9
|
emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b062266b8e
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emit_x64_vector: More explicit lambda decay
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
3afd2fcbad
|
A64: Implement MUL (vector)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b6de612e01
|
IR: Implement VectorMultiply
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
90a053a5e4
|
emit_x64_vector: Order alphabetically
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e7041d7196
|
A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a455ff70c9
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decoder/a64: Don't rearrange unrelated decoders
|
2020-04-22 20:46:14 +01:00 |
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