MerryMage
|
e4697b1676
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A64: Implement system register TPIDR_EL0
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
e3da92024e
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A64: Implement system registers FPCR and FPSR
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
9e4e4e9c1d
|
A64: Implement system register CNTPCT_EL0
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
1e15283d00
|
A64: Implement system register CTR_EL0
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
58fbb3ff1b
|
A64: Implement NEG (vector)
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
710d09471b
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IR: Add IR instruction ZeroVector
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
2721bb5ace
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emit_x64_floating_point: Add maybe_unused to preprocess parameter
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
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0575e7421b
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1c9804ea07
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A64: Implement FMAXNM (scalar)
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2020-04-22 20:46:15 +01:00 |
|
MerryMage
|
1dfce0894d
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constant_pool: Add frame parameter
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bd2b415850
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A64: Implement ADDP (scalar)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
84f1c9b7f4
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reg_alloc: Only exchange GPRs
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9df3793af0
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A64: Implement DUP (element), scalar variant
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2020-04-22 20:46:14 +01:00 |
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MerryMage
|
6541ec064d
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emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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2080a51f41
|
A64: Implement FMAX (scalar), FMIN (scalar)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
44a5b57f2a
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fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
eaa1fd36a7
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travis: Switch unicorn repository
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
7c193485e1
|
a64/config: Allow NaN emulation accuracy to be set
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a3df46a75a
|
a64_emit_x64: Add conf to A64EmitContext
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1311f67b4a
|
fuzz_with_unicorn: Explicitly test floating point instructions
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
0e157b0198
|
A64: Implement FSQRT (scalar)
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
07520f32c3
|
backend_x64: Accurately handle NaNs
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e97581d063
|
fuzz_with_unicorn: Print AArch64 disassembly
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
01c1e9017e
|
T32: Add initial decoder list
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ccf7df057b
|
simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8cebb87d0d
|
A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
7f68d556ab
|
decoder/a64: Rearrange SIMD two-register misc decoders
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
d5af052f06
|
A64: Implement CMGE (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9d85991906
|
A64: Implement CMHI, CMHS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
e2b9b7c5b0
|
IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned}
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
0df6725f73
|
A64: Implement SMAX, SMIN, UMAX, UMIN
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
47c0ad0fc8
|
IR: Implement Vector{Max,Min}{Signed,Unsigned}
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
adb7f5f86f
|
A64: Implement CMGT (register)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f4775910f5
|
IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
1f5b3bca43
|
Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f3fa4a042f
|
a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9f04f2c892
|
Merge branch 'feature/exclusive-mem'
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f6a2104ab3
|
fuzz_with_unicorn: Speed up tests by not initializing/tearing down constantly
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8698f057d0
|
A64: Implement STXP, STLXP, LDXP, LDAXP
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a38f35eef6
|
Merge branch 'feature/direct-page-table-access'
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
2a6619d59c
|
A64: Implement CLREX
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
9f2f08db8d
|
a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
a6cc667509
|
Direct Page Table Access: Handle address spaces less than the full 64-bit in size
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
b7a2c1a7df
|
A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
6c4773e85b
|
abi: Add RAX to ABI_ALL_CALLER_SAVE
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
f45a5e17c6
|
Implement direct page table access
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
8756487554
|
A64: Partially implement MRS
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
ef02658049
|
fuzz_with_unicorn: Fix read-past-end access via jit_iter
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd65bedfe
|
A64: Implement DSB, DMB
|
2020-04-22 20:46:14 +01:00 |
|
MerryMage
|
bfd3e30c75
|
callbacks: Member functions should be const
|
2020-04-22 20:46:14 +01:00 |
|