Lioncash
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eb2d28d2b1
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emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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49cc6d7fad
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A64: Implement FDIV (vector)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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c832cec96d
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Correct FPSR and FPCR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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147284427b
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A64: Implement USHL
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e4697b1676
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A64: Implement system register TPIDR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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e3da92024e
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A64: Implement system registers FPCR and FPSR
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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9e4e4e9c1d
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A64: Implement system register CNTPCT_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1e15283d00
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A64: Implement system register CTR_EL0
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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710d09471b
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IR: Add IR instruction ZeroVector
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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2721bb5ace
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emit_x64_floating_point: Add maybe_unused to preprocess parameter
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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0575e7421b
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A64: Implement FMINNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1c9804ea07
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A64: Implement FMAXNM (scalar)
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2020-04-22 20:46:15 +01:00 |
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MerryMage
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1dfce0894d
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constant_pool: Add frame parameter
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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84f1c9b7f4
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reg_alloc: Only exchange GPRs
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6541ec064d
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emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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7c193485e1
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a64/config: Allow NaN emulation accuracy to be set
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a3df46a75a
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a64_emit_x64: Add conf to A64EmitContext
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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07520f32c3
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backend_x64: Accurately handle NaNs
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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e97581d063
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fuzz_with_unicorn: Print AArch64 disassembly
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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47c0ad0fc8
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IR: Implement Vector{Max,Min}{Signed,Unsigned}
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f4775910f5
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IR: Implement VectorGreaterSigned
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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1f5b3bca43
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Exclusive fixups
* Incorrect size of exclusive_address
* Disable tests on exclusive memory instructions for now
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f3fa4a042f
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a64_emit_x64: EmitExclusiveWrite: Make MSVC happy (narrowing conversion warning)
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8698f057d0
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A64: Implement STXP, STLXP, LDXP, LDAXP
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b7a2c1a7df
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A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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a6cc667509
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Direct Page Table Access: Handle address spaces less than the full 64-bit in size
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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f45a5e17c6
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Implement direct page table access
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bfd3e30c75
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callbacks: Member functions should be const
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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9f2f08db8d
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a64_emit_x64: Implement {Read,Write}Memory128 in terms of a function call
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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6c4773e85b
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abi: Add RAX to ABI_ALL_CALLER_SAVE
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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8756487554
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A64: Partially implement MRS
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bfd65bedfe
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A64: Implement DSB, DMB
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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5edd623b9d
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Implement DC instructions
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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2cb0a699ba
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IR: Implement FPMax, FPMin
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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98c8e7d1af
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IR: Implement FPVectorAdd
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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eae518a338
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IR: Implement VectorSignExtend
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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b9cd345ddc
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IR: Implement FPVectorSub
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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851fc83445
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emit_x64_vector: EmitOneArgumentFallback
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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303088a51e
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IR: Implement VectorPopulationCount
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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bf2cd92da9
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emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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b062266b8e
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emit_x64_vector: More explicit lambda decay
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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b6de612e01
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IR: Implement VectorMultiply
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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90a053a5e4
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emit_x64_vector: Order alphabetically
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2020-04-22 20:46:14 +01:00 |
|
MerryMage
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715ae1c229
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IR: Implement VectorArithmeticShiftRight
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2020-04-22 20:46:14 +01:00 |
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MerryMage
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132c783320
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IR: Implement VectorNarrow
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1423584f9f
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constant_pool: Allow for 128-bit constants
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
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69de50a878
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emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
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cbc9f361b0
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IR: Implement VectorSub
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
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b22c5961f9
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IR: Implement VectorLogicalShiftRight
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2020-04-22 20:46:13 +01:00 |
|
MerryMage
|
59ace60b03
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IR: Implement VectorZeroExtend
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2020-04-22 20:46:13 +01:00 |
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