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  • a6c6539109 A64: Implement CCMP (register) Lioncash 2018-02-04 19:09:20 -0500
  • 22632db337 microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement Lioncash 2018-02-04 19:38:47 -0500
  • c5033b5dda A64: Implement CCMN (register) MerryMage 2018-02-04 23:08:16 +0000
  • dd2a6684fe IR: Add ConditionalSelectNZCV instruction MerryMage 2018-02-04 23:07:51 +0000
  • 12c6f841c2 inst_gen: Make invalid_instructions a static inline variable Lioncash 2018-02-04 14:35:22 -0500
  • f96e83c486 fuzz_with_unicorn: Move instruction generator vector into GenRandomInst Lioncash 2018-02-04 14:33:34 -0500
  • 4491746eae A64: Implement FNEG MerryMage 2018-02-04 13:44:33 +0000
  • db958061a3 A64: Implement FABS MerryMage 2018-02-04 13:43:47 +0000
  • 8765b421b7 A64: Implement FCSEL MerryMage 2018-02-04 13:40:37 +0000
  • 7e82d8eede A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer) MerryMage 2018-02-04 13:21:31 +0000
  • 2409e5d082 A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer) MerryMage 2018-02-04 13:08:25 +0000
  • b173fcf34e backend_x64: Simplify FPDoubleToU32 and FPSingleToU32 MerryMage 2018-02-04 13:07:19 +0000
  • 56bc7825ef A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register) MerryMage 2018-02-04 12:18:57 +0000
  • d040920727 Common: Put AES code within its own nested namespace Lioncash 2018-02-03 17:48:50 -0500
  • 40614202e7 A64: Implement AESD Lioncash 2018-02-03 17:20:21 -0500
  • ccef85dbb7 A64: Implement AESE Lioncash 2018-02-03 13:16:02 -0500
  • 68f46c8334 backend_x64: Use a reference to BlockOfCode instead of a pointer MerryMage 2018-02-03 14:28:57 +0000
  • 8931ee346b IR: Add IR instruction NZCVFromPackedFlags MerryMage 2018-02-03 13:34:40 +0000
  • 0bb4474fb9 A64: Implement INS (general) MerryMage 2018-02-03 13:07:00 +0000
  • d13704fdef A64: Implement INS (element) MerryMage 2018-02-03 13:03:50 +0000
  • 0642d49919 A64: Implement SMOV MerryMage 2018-02-03 12:58:19 +0000
  • 5297027ebe A64: Implement UMOV MerryMage 2018-02-03 12:55:53 +0000
  • 47661b746b basic_block: Fix bogus GCC maybe-uninitialized warning MerryMage 2018-02-03 03:04:44 +0000
  • 1fb0957aa3 A64: Implement FCVT MerryMage 2018-02-03 01:23:11 +0000
  • ca38225e08 fuzz_with_unicorn: Skip instructions that need to be interpreted MerryMage 2018-02-03 01:22:40 +0000
  • 4be55b8b84 A64: Implement FMOV (scalar, immediate) MerryMage 2018-02-03 00:52:48 +0000
  • a07c05ea51 A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP) MerryMage 2018-02-02 22:39:24 +0000
  • 93fcbdf1e2 A64: Implement FCMP, FCMPE MerryMage 2018-02-02 22:25:51 +0000
  • 75b8a76630 a64_jitstate: A64 does not have a seperate FPSCR.NZCV MerryMage 2018-02-02 22:25:18 +0000
  • 99d8ebe4d5 A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar) MerryMage 2018-02-02 22:04:09 +0000
  • 429dc24587 IR: Merge U32 and U64 variants of FP instructions MerryMage 2018-02-02 21:55:23 +0000
  • ed2bedec43 A64: Implement {ST,LD}{1,2,3,4} (multiple structures) MerryMage 2018-02-02 21:07:51 +0000
  • 6414736a8d emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1 MerryMage 2018-02-02 21:07:00 +0000
  • ebfc51c609 IR: Implement VectorSetElement{8,16,32,64} MerryMage 2018-02-02 21:00:12 +0000
  • a5c4fbc783 A64: Implement AESIMC and AESMC Lioncash 2018-01-30 07:56:18 -0500
  • 744495e23d iterator_util: Make Reverse constexpr Lioncash 2018-01-31 10:01:55 -0500
  • ab9b5fb8aa Common: Relocate common bits of CRC32 Lioncash 2018-01-29 12:31:50 -0500
  • af1384d700 A64: Implement CRC32 Lioncash 2018-01-28 01:41:58 -0500
  • 01b4395bf8 travis: Bump MACOSX_DEPLOYMENT_TARGET MerryMage 2018-01-29 17:05:50 +0000
  • 7e0f14303c fuzz_with_unicorn: Print information on test failure MerryMage 2018-01-28 17:57:32 +0000
  • 64761dbc72 scope_exit: Add SCOPE_SUCCESS and SCOPE_EXIT MerryMage 2018-01-28 17:57:02 +0000
  • bafb39ebc5 A64: Add Disassemble method MerryMage 2018-01-28 17:56:26 +0000
  • cc0eb18a0b A32: data_processing: Remove !S assertions MerryMage 2018-01-28 12:58:33 +0000
  • 865a30eb0d A32: Implement BKPT MerryMage 2018-01-28 12:56:00 +0000
  • f023bbb893 A32: Add ExceptionRaised IR instruction and use it MerryMage 2018-01-28 12:55:47 +0000
  • 7ffbebf290 A64: Implement CRC32C Lioncash 2018-01-25 12:51:45 -0500
  • d7044bc751 assert: Use fmt in ASSERT_MSG MerryMage 2018-01-27 23:42:30 +0000
  • b60c7f31c1 externals: Update catch to v2.1.1 Lioncash 2018-01-27 15:40:10 -0500
  • 71422c2b48 fuzz_with_unicorn: Move data outside loop Lioncash 2018-01-27 15:06:55 -0500
  • cd69c6a17c fuzz_with_unicorn: Dehardcode some constants Lioncash 2018-01-27 14:58:49 -0500
  • 52268298a8 a64_emit_x64: Perform RSB predictions MerryMage 2018-01-27 22:44:17 +0000
  • 98ec9c5f90 A32: Change UserCallbacks to be similar to A64's interface MerryMage 2018-01-27 22:36:55 +0000
  • b9ce660113 reg_alloc: std::move RegAlloc's function argument Lioncash 2018-01-26 21:35:42 -0500
  • ed561d6653 General: Add missing override specifiers Lioncash 2018-01-26 21:25:27 -0500
  • b2d99eddc6 EmitZeroExtendLongToQuad: Do not rely on register allocator to zero extend 64->128 MerryMage 2018-01-27 01:59:14 +0000
  • f4f774f9f6 a64_get_set_elimination_pass: Simplify algorithm MerryMage 2018-01-27 01:33:04 +0000
  • 54de64f5bf a64_emit_x64: bug: x64 sign-extends 32-bit immediates MerryMage 2018-01-27 00:38:09 +0000
  • 6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass MerryMage 2018-01-26 23:37:54 +0000
  • e01b500aea ir_emitter: Allow the insertion point for new instructions to be set MerryMage 2018-01-26 23:30:17 +0000
  • af793c2527 {a32,a64}_interface: Predict entrypoint MerryMage 2018-01-26 22:54:03 +0000
  • 7734cf1050 A64: Implement EXTR Lioncash 2018-01-26 11:49:08 -0500
  • e1fd6038a2 externals: Update xbyak to v5.601 MerryMage 2020-04-22 20:45:52 +0100
  • 9fb82036ca Squashed 'externals/xbyak/' changes from d512551e..2794cde7 MerryMage 2020-04-22 20:45:52 +0100
  • 88ae7fce52 A64: Implement LDP (SIMD&FP) and STP (SIMD&FP) MerryMage 2018-01-26 18:36:33 +0000
  • d497464c9f a64_jitstate: Have 128-bit wide spills MerryMage 2018-01-26 18:35:46 +0000
  • b513b2ef05 IR: Implement IR instructions A64{Get,Set}S MerryMage 2018-01-26 18:35:19 +0000
  • 16fa2cd8f6 a64_emit_x64: Use xword from Xbyak::util MerryMage 2018-01-26 18:34:22 +0000
  • 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable Lioncash 2018-01-26 08:51:48 -0500
  • 7abd673a49 A64: Zero upper 64 bits in ORN if using the 64-bit variant Lioncash 2018-01-26 12:00:27 -0500
  • d3b1a72bca unicorn: Display EC and ISS separately beside the full ESR value Lioncash 2018-01-25 21:49:21 -0500
  • 8fa9849c25 unicorn: Use static_cast instead of reinterpret_cast Lioncash 2018-01-25 22:40:05 -0500
  • ba3d6da0c8 load_store_register_unprivileged: bug: LDTRSW MerryMage 2018-01-26 02:03:16 +0000
  • 75756137c6 A64: Implement CMEQ (register, vector) MerryMage 2018-01-26 01:52:42 +0000
  • d5283e46e8 IR: Implement IR instructions VectorEqual{8,16,32,64,128} MerryMage 2018-01-26 01:52:06 +0000
  • 4ce9c65cfb reg_alloc: Use std::exchange MerryMage 2018-01-26 01:51:04 +0000
  • e0c12ec2ad A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142) Fernando Sahmkow 2018-01-25 20:57:56 -0400
  • cf824fb2b2 unicorn_load: Minor Windows-related changes Lioncash 2018-01-25 19:47:25 -0500
  • a8ed248a13 tests/A64: Test memory writes MerryMage 2018-01-25 23:56:57 +0000
  • 94383fd934 microinstruction: Missed A64{Read,Write}Memory128 from opcode information MerryMage 2018-01-25 23:56:14 +0000
  • d124a1d761 emit_x64_packed: EmitPackedSubU16 modified xmm_b wasn't writeable MerryMage 2018-01-25 18:37:03 +0000
  • f1057aa362 tests: Fix truncation in GetFpcr() Lioncash 2018-01-25 13:06:56 -0500
  • 589ad7232f Fixup: Xn|SP are 64 bit addresses encoded in the Rn field James Rowe 2018-01-23 22:16:07 -0700
  • ae880d8391 A64: Fix bugs and address review comments James Rowe 2018-01-22 23:21:17 -0700
  • 3aeb7ca50c Add missing returns James Rowe 2018-01-22 09:35:33 -0700
  • 41e6e659c5 A64: Implement Load/Store register (unprivileged) James Rowe 2018-01-22 00:37:27 -0700
  • 01a26fa644 fixup: travis: Test with disabled CPU feature detection MerryMage 2018-01-24 19:14:19 +0000
  • 5281d3c6d5 CMakeLists: Add opcodes.inc to the source file list Lioncash 2018-01-24 14:37:11 -0500
  • 30936f5e94 travis: Test with disabled CPU feature detection MerryMage 2018-01-24 19:14:19 +0000
  • 285fd22c30 IR: Add IR instruction VectorZeroUpper MerryMage 2018-01-24 17:11:13 +0000
  • da3e9a5704 a64_emit_x64: bug: EmitA64WriteMemory128 should write not read MerryMage 2018-01-24 16:49:06 +0000
  • ab84524806 Implemented SDIV and UDIV instructions FernandoS27 2018-01-24 08:36:39 -0400
  • 6033b05ca6 A64: Implement LDR/STR (immediate, SIMD&FP) MerryMage 2018-01-24 15:57:03 +0000
  • f698848e26 IR: Add IR instructions A64Memory{Read,Write}128 MerryMage 2018-01-24 16:18:24 +0000
  • e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 MerryMage 2018-01-24 15:55:59 +0000
  • e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} MerryMage 2018-01-24 15:54:56 +0000
  • 28ccd85e5c IR: Add IR instruction ZeroExtendToQuad MerryMage 2018-01-24 15:54:11 +0000
  • af848c627d block_of_code: Add ABI_RETURN2 MerryMage 2018-01-24 15:53:12 +0000
  • 1749780929 interface: Move Vector typedef to config.h MerryMage 2018-01-24 15:52:49 +0000
  • 33bba6028c bit_util: bug: Infinite loop in HighestSetBit MerryMage 2018-01-24 16:15:17 +0000
  • 3caf192f60 A64: Implement DUP (general) MerryMage 2018-01-24 12:00:56 +0000