Lioncash
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ccef85dbb7
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A64: Implement AESE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0bb4474fb9
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A64: Implement INS (general)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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d13704fdef
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A64: Implement INS (element)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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0642d49919
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A64: Implement SMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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5297027ebe
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A64: Implement UMOV
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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1fb0957aa3
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A64: Implement FCVT
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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4be55b8b84
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A64: Implement FMOV (scalar, immediate)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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a07c05ea51
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A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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93fcbdf1e2
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A64: Implement FCMP, FCMPE
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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99d8ebe4d5
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A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar)
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2020-04-22 20:46:13 +01:00 |
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MerryMage
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ed2bedec43
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A64: Implement {ST,LD}{1,2,3,4} (multiple structures)
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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a5c4fbc783
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A64: Implement AESIMC and AESMC
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2020-04-22 20:46:13 +01:00 |
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Lioncash
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af1384d700
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A64: Implement CRC32
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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7ffbebf290
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A64: Implement CRC32C
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2020-04-22 20:46:12 +01:00 |
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Lioncash
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7734cf1050
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A64: Implement EXTR
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2020-04-22 20:46:12 +01:00 |
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MerryMage
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88ae7fce52
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A64: Implement LDP (SIMD&FP) and STP (SIMD&FP)
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2020-04-22 20:44:38 +01:00 |
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Lioncash
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67443efb62
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General: Convert multiple namespace specifiers to nested namespace specifiers where applicable
Makes namespacing a little less noisy
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2020-04-22 20:44:38 +01:00 |
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MerryMage
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75756137c6
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A64: Implement CMEQ (register, vector)
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2020-04-22 20:44:38 +01:00 |
|
Fernando Sahmkow
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e0c12ec2ad
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A64: Implemented EOR (vector), ORR (vector, register) and ORN (vector) Instructions (#142)
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2020-04-22 20:44:38 +01:00 |
|
James Rowe
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ae880d8391
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A64: Fix bugs and address review comments
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2020-04-22 20:44:38 +01:00 |
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James Rowe
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41e6e659c5
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A64: Implement Load/Store register (unprivileged)
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2020-04-22 20:44:37 +01:00 |
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FernandoS27
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ab84524806
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Implemented SDIV and UDIV instructions
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
6033b05ca6
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A64: Implement LDR/STR (immediate, SIMD&FP)
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
3caf192f60
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A64: Implement DUP (general)
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2020-04-22 20:44:37 +01:00 |
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Lioncash
|
6f9216d544
|
A64: Implement RBIT
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2020-04-22 20:44:37 +01:00 |
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MerryMage
|
d4b05b28cf
|
A64: Implement CLS
This is not the cleanest implementation.
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
b8e26bfdc3
|
A64: Implement ADDP (vector)
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
bb1c5bd3b2
|
A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
c1a25bfc2f
|
A64: Implement MADD and MSUB
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
b7c5055d42
|
A64: Implement CLZ
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
ae5dbcbed6
|
A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL
Truly the most difficult A64 instructions to implement.
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2020-04-22 20:42:46 +01:00 |
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Lioncash
|
4d8f4aa8af
|
A64: Implement ASRV, LSLV, LSRV, and RORV
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2020-04-22 20:42:46 +01:00 |
|
Lioncash
|
a8a65beb2b
|
data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
f81d0a2536
|
A64: Implement AND (vector)
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2020-04-22 20:42:46 +01:00 |
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MerryMage
|
a63fc6c89b
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A64: Implement ADD (vector, vector)
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2020-04-22 20:42:46 +01:00 |
|
Thomas Guillemard
|
896cf44f96
|
A64: Implement REV, REV32, and REV16 (#126)
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2020-04-22 20:42:46 +01:00 |
|
MerryMage
|
144b629d8a
|
A64: Implement CSEL
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
9f57283a30
|
A64: Implement SBFM, BFM, UBFM
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2020-04-22 20:42:45 +01:00 |
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MerryMage
|
cdbc8d07a5
|
A64: Implement MOVN, MOVZ, MOVK
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
b34c6616d4
|
A64/decoder: Split decoder data from header
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
243f06c613
|
A64: Implement LDP, STP
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
25411da838
|
A32: Implement load stores (immediate)
|
2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
68391b0a05
|
A64: Implement SVC
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
cb481a3a48
|
A64: Implement compare and branch
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
23f3afe0b3
|
A64: Implement branch (register)
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
86d1095df7
|
A64: Implement branch
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
0641445e51
|
A64: Implement logical
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
5a1d88c5dc
|
A64: Implement pcrel
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2020-04-22 20:42:45 +01:00 |
|
MerryMage
|
c09e69bb97
|
A64: Implement addsub instructions
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2020-04-22 20:42:44 +01:00 |
|
MerryMage
|
d1cef6ffb0
|
A64: Implement ADD_shifted
|
2020-04-22 20:42:44 +01:00 |
|
MerryMage
|
e161cf16f5
|
A64: Initial framework
|
2020-04-22 20:42:44 +01:00 |
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